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Spartan-3E FPGA Family: Complete Data Sheet
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DS312 March 21, 2005
Module 1: Introduction and Ordering Information
DS312-1 (v1.1) March 21, 2005 6 pages * * * * * Introduction Features Architectural Overview Package Marking Ordering Information
Module 3: DC and Switching Characteristics
DS312-3 (v1.0) March 1, 2005 18 pages * DC Electrical Characteristics - Absolute Maximum Ratings - Supply Voltage Specifications - Recommended Operating Conditions - DC Characteristics Switching Characteristics - DCM Timing - Configuration and JTAG Timing
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Module 2: Functional Description
DS312-2 (v1.1) March 21, 2005 96 pages * Input/Output Blocks (IOBs) - Overview - SelectIOTM Signal Standards Configurable Logic Block (CLB) Block RAM Dedicated Multipliers Digital Clock Manager (DCM) Clock Network Configuration Powering Spartan-3E FPGAs
Module 4: Pinout Descriptions
DS312-4 (v1.1) March 21, 2005 72 pages * * * * Pin Descriptions Package Overview Pinout Tables Footprint Diagrams
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IMPORTANT NOTE: The SpartanTM-3E FPGA data sheet is created and published in separate modules. This complete version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy navigation in this volume.
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Spartan-3E FPGA Family: Introduction and Ordering Information
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Advance Product Specification
Introduction
The SpartanTM-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The five-member family offers densities ranging from 100,000 to 1.6 million system gates, as shown in Table 1. The Spartan-3E family builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration. These Spartan-3E enhancements, combined with advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry. Because of their exceptionally low cost, Spartan-3E FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment. The Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs. - True LVDS, RSDS, mini-LVDS differential I/O - 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling - Enhanced Double Data Rate (DDR) support Abundant, flexible logic resources - Densities up to 33,192 logic cells, including optional shift register or distributed RAM support - Efficient wide multiplexers, wide logic - Fast look-ahead carry logic - Enhanced 18 x 18 multipliers with optional pipeline - IEEE 1149.1/1532 JTAG programming/debug port Hierarchical SelectRAMTM memory architecture - Up to 648 Kbits of fast block RAM - Up to 231 Kbits of efficient distributed RAM Up to eight Digital Clock Managers (DCMs) - Clock skew elimination (delay locked loop) - Frequency synthesis, multiplication, division - High-resolution phase shifting - Wide frequency range (5 MHz to over 300 MHz) Eight global clocks and eight clocks for each half of device, plus abundant low-skew routing Configuration interface to industry-standard PROMs - Low-cost, space-saving SPI serial Flash PROM - x8 or x8/x16 parallel NOR Flash PROM - Low-cost Xilinx Platform Flash with JTAG Complete Xilinx ISETM, WebPACKTM development system support MicroBlazeTM, PicoBlazeTM embedded processor cores Fully compliant 32-/64-bit 33/66 MHz PCI support Low-cost QFP and BGA packaging options - Common footprints support easy density migration - Pb-free packaging options
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Features
* * * Very low cost, high-performance logic solution for high-volume, consumer-oriented applications Proven advanced 90-nanometer process technology Multi-voltage, multi-standard SelectIOTM interface pins - Up to 376 I/O pins or 156 differential signal pairs - LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards * * * *
Table 1: Summary of Spartan-3E FPGA Attributes
Equivalent Logic Cells 2,160 5,508 10,476 19,512 33,192 CLB Array (One CLB = Four Slices) Rows Columns 22 34 46 60 76 16 26 34 46 58 Total CLBs 240 612 1,164 2,168 3,688 Total Slices 960 2,448 4,656 8,672 14,752 Distributed RAM bits(1) 15K 38K 73K 136K 231K Block RAM bits(1) 72K 216K 360K 504K 648K Maximum Differential I/O Pairs 40 68 92 124 156
Device XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E
System Gates 100K 250K 500K 1200K 1600K
Dedicated Multipliers DCMs 4 12 20 28 36 2 4 4 8 8
Maximum User I/O 108 172 232 304 376
Notes: 1. By convention, one Kb is equivalent to 1,024 bits.
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Introduction and Ordering Information
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Architectural Overview
The Spartan-3E family architecture consists of five fundamental programmable functional elements: * Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data. Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB supports bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including four high-performance differential standards. Double Data-Rate (DDR) registers are included. Block RAM provides data storage in the form of 18-Kbit dual-port blocks. Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product. * Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals.
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These elements are organized as shown in Figure 1. A ring of IOBs surrounds a regular array of CLBs. Each device has two columns of block RAM except for the XC3S100E, which has one column. Each RAM column consists of several 18-Kbit RAM blocks. Each block RAM is associated with a dedicated multiplier. The DCMs are positioned in the center with two at the top and two at the bottom of the device. The XC3S100E has only one DCM at the top and bottom, while the XC3S1200E and XC3S1600E add two DCMs in the middle of the left and right sides. The Spartan-3E family features a rich network of traces that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing.
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Notes:
1. The XC3S1200E and XC3S1600E have two additional DCMs on both the left and right sides as indicated by the dashed lines. The XC3S100E has only one DCM at the top and one at the bottom.
Figure 1: Spartan-3E Family Architecture
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Introduction and Ordering Information
Configuration
Spartan-3E FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA's configuration data is stored externally in a PROM or some other non-volatile medium, either on or off the board. After applying power, the configuration data is written to the FPGA using any of seven different modes: * * * * * * Master Serial from a Xilinx Platform Flash PROM Serial Peripheral Interface (SPI) from an industry-standard SPI serial Flash Byte Peripheral Interface (BPI) Up or Down from an industry-standard x8 or x8/x16 parallel NOR Flash Slave Serial, typically downloaded from a processor Slave Parallel, typically downloaded from a processor Boundary Scan (JTAG), typically downloaded from a processor or system tester.
I/O Capabilities
The Spartan-3E FPGA SelectIO interface supports many popular single-ended and differential standards. Table 2 shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination. Spartan-3E FPGAs support the following single-ended standards: * * * * * 3.3V, low-voltage TTL, LVTTL Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V 3.3V PCI at 33 MHz and 66 MHz HSTL I and III at 1.8V, typically for memory applications SSTL I at 1.8V and 2.5V, typically for memory applications
Spartan-3E FPGAs support the following differential standards: * * * * LVDS Bus LVDS mini-LVDS RSDS
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
VQ100 VQG100 Device XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E Notes:
1. All Spartan-3E devices in the same package are pin-compatible.
CP132 CPG132 User 92 92 Diff 41 41 -
TQ144 TQG144 User 108 108 Diff 40 40 -
PQ208 PQG208 User 158 158 Diff 65 65 -
FT256 FTG256 User 172 190 190 Diff 68 77 77 -
FG320 FGG320 User 232 250 250 Diff 92 99 99
FG400 FGG400 User 304 304 Diff 124 124
FG484 FGG484 User 376 Diff 156
User 66 66 -
Diff 30 30 -
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Package Marking
Figure 2 provides a top marking example for Spartan-3E FPGAs in the quad-flat packages. Figure 3 shows the top marking for Spartan-3E FPGAs in BGA packages except the 132-ball chip-scale package (CP132 and CPG132). The markings for the BGA packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball A1 indicator. Figure 4 shows the top marking for Spartan-3E FPGAs in the CP132 and CPG132 packages. Use the seven digits of the Lot Code to access additional information for a specific device using the Xilinx web-based Genealogy Viewer.
Mask Revision Code Fabrication Code
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SPARTAN
Device Type Package Speed Grade Temperature Range
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Process Technology Date Code Lot Code
XC3S250E TM PQ208AGQ0525 D1234567A 4C
Pin P1
DS312-1_06_032105
Figure 2: Spartan-3E QFP Example Package Marking
Mask Revision Code
BGA Ball A1 Device Type Package
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SPARTAN
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Fabrication Code Process Code
XC3S250ETM FT256AGQ0525 D1234567A 4C
Date Code Lot Code
Speed Grade Temperature Range
DS312-1_02_032105
Figure 3: Spartan-3E BGA Example Package Marking
Ball A1 Lot Code
3S250E F1234567-0525 PHILIPPINES
Device Type Date Code Temperature Range
Package C5 = CP132 C6 = CPG132
C5AGQ
4C
Speed Grade Process Code Fabrication Code
DS312-1_05_032105
Mask Revision Code
Figure 4: Spartan-3E CP132 and CPG132 Example Package Marking
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Introduction and Ordering Information
Ordering Information
Spartan-3E FPGAs are available in both standard and Pb-free packaging options for all device/package combinations. The Pb-free packages include a `G' character in the ordering code.
Standard Packaging
Example:
Device Type Speed Grade Package Type
XC3S250E -4 FT 256 C
Temperature Range: C = Commercial (TJ = 0oC to 85oC) I = Industrial (TJ = -40oC to 100oC) Number of Pins
DS312_03_011405
Pb-Free Packaging
Example:
Device Type Speed Grade Package Type
XC3S250E -4 FT G 256 C
Temperature Range: C = Commercial (TJ = 0oC to 85oC) I = Industrial (TJ = -40oC to 100oC) Number of Pins Pb-free DS312_04_011405
Device XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E
Speed Grade -4 Standard Performance -5 High Performance
Package Type / Number of Pins VQ(G)100 100-pin Very Thin Quad Flat Pack (VQFP) CP(G)132 132-ball Chip-Scale Package (CSP) TQ(G)144 144-pin Thin Quad Flat Pack (TQFP) PQ(G)208 208-pin Plastic Quad Flat Pack (PQFP) FT(G)256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA) FG(G)320 320-ball Fine-Pitch Ball Grid Array (FBGA) FG(G)400 400-ball Fine-Pitch Ball Grid Array (FBGA) FG(G)484 484-ball Fine-Pitch Ball Grid Array (FBGA)
Temperature Range (TJ ) C Commercial (0C to 85C) I Industrial (-40C to 100C)
Notes:
1. The -5 speed grade is exclusively available in the Commercial temperature range.
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Revision History
The following table shows the revision history for this document. Date 03/01/05 03/21/05 Version 1.0 1.1 Initial Xilinx release. Added XC3S250E in CP132 package to Table 2. Corrected number of differential I/O pairs for CP132 package. Added package markings for QFP packages (Figure 2) and CP132/CPG132 packages (Figure 4). Revision
The Spartan-3E Family Data Sheet
DS312-1, Spartan-3E FPGA Family: Introduction and Ordering Information (Module 1) DS312-2, Spartan-3E FPGA Family: Functional Description (Module 2) DS312-3, Spartan-3E FPGA Family: DC and Switching Characteristics (Module 3) DS312-4, Spartan-3E FPGA Family: Pinout Descriptions (Module 4)
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Spartan-3E FPGA Family: Functional Description
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification the delay element, there are alternate routes through a pair of storage elements to the IQ1 and IQ2 lines. The IOB outputs I, IQ1, and IQ2 lead to the FPGA's internal logic. The delay element can be set to ensure a hold time of zero (see Input Delay Functions). The output path, starting with the O1 and O2 lines, carries data from the FPGA's internal logic through a multiplexer and then a three-state driver to the IOB pad. In addition to this direct path, the multiplexer provides the option to insert a pair of storage elements. The 3-state path determines when the output driver is high impedance. The T1 and T2 lines carry data from the FPGA's internal logic through a multiplexer to the output driver. In addition to this direct path, the multiplexer provides the option to insert a pair of storage elements. All signal paths entering the IOB, including those associated with the storage elements, have an inverter option. Any inverter placed on these paths is automatically absorbed into the IOB.
Introduction
As described in Architectural Overview, the SpartanTM-3E FPGA architecture consists of five fundamental functional elements: * * * * * Input/Output Blocks (IOBs) Configurable Logic Block (CLB) and Slice Resources Block RAM Dedicated Multipliers Digital Clock Managers (DCMs) *
*
The following sections provide detailed information on each of these functions. In addition, this section also describes the following functions: * * * * Clocking Infrastructure Interconnect Configuration Powering Spartan-3E FPGAs *
Input/Output Blocks (IOBs)
IOB Overview
The Input/Output Block (IOB) provides a programmable, unidirectional or bidirectional interface between a package pin and the FPGA's internal logic. The IOB is similar to that of the Spartan-3 family with the following differences: * * * Input-only blocks are added Programmable input delays are added to all blocks DDR flip-flops can be shared between adjacent IOBs
The unidirectional input-only block has a subset of the full IOB capabilities. Thus there are no connections or logic for an output path. The following paragraphs assume that any reference to output functionality does not apply to the input-only blocks. The number of input-only blocks varies with device size, but is never more than 25% of the total IOB count. Figure 1, page 2 is a simplified diagram of the IOB's internal structure. There are three main signal paths within the IOB: the output path, input path, and 3-state path. Each path has its own pair of storage elements that can act as either registers or latches. For more information, see Storage Element Functions. The three main signal paths are as follows: * The input path carries data from the pad, which is bonded to a package pin, through an optional programmable delay element directly to the I line. After
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Functional Description
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T T1
D CE CK SR
Q
TFF1
REV DDR MUX
TCE T2
D CE CK SR
Q TFF2
REV
Three-state Path
ODDROUT1 O1 ODDRIN1 OTCLK1 D CE CK SR OCE O2 ODDRIN2 OTCLK2 D CE CK SR REV
Keeper Latch
Q
OFF1
VCCO
Pull-Up REV
DDR MUX
ESD
I/O Pin
Q OFF2
Programmable Output Driver
PullDown
ESD
ODDROUT2 I IQ1 IDDRIN1 IDDRIN2 ICLK1 ICE D CE CK SR REV Q IFF1
Output Path
LVCMOS, LVTTL, PCI Programmable Delay Single-ended Standards using VREF VREF Pin Differential Standards
IQ2 D CE ICLK2 SR REV Input Path CK SR REV Q IFF2
I/O Pin from Adjacent IOB
DS312-2_19_030105
Notes:
1. 2. All IOB signals communicating with the FPGA's internal logic have the option of inverting polarity inside the IOB. Signals shown with dashed lines connect to the adjacent IOB in a differential pair only, not to the FPGA fabric.
Figure 1: Simplified IOB Diagram
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Functional Description The delay values are set up in the silicon once at configuration time--they are non-modifiable in device operation. The primary use for the input delay element is as an adequate delay to ensure that there is no hold time requirement when using the input flip-flop(s) with a global clock. The necessary value for this function is chosen by the Xilinx software tools and depends on device size. If the design is using a DCM in the clock path, then the delay element can be safely set to zero in the user's design, and there is still no hold time requirement. Both asynchronous and synchronous values can be modified by the user, which is useful where extra delay is required on clock or data inputs, for example, in interfaces to various types of RAM. See Module 3 of the Spartan-3E data sheet for exact values for the delay elements.
Synchronous input (IQ1) DQ Synchronous input (IQ2) DQ
Input Delay Functions
Each IOB has a programmable delay block that can delay the input signal from 0 to nominally 4000 ps. In Figure 2, the signal is first delayed by either 0 or 2000 ps (nominal) and is then applied to an 8 tap delay line. This delay line has a nominal value of 250 ps per tap. All 8 taps are available via a multiplexer for use as an asynchronous input directly into the FPGA fabric. In this way, the delay is programmable from 0 to 4000 ps in 250 ps steps. Four of the 8 taps are also available via a multiplexer to the D inputs of the synchronous storage elements. The delay inserted in the path to the storage element can be varied from 0 to 4000 ps in 500 ps steps. The first, coarse delay element is common to both asynchronous and synchronous paths, and must be either used or not used for both paths.
PAD
Asynchronous input (I)
DS312-2_18_022205
Figure 2: Input Delay Elements
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Storage Element Functions
There are three pairs of storage elements in each IOB, one pair for each of the three paths. It is possible to configure each of these storage elements as an edge-triggered D-type flip-flop (FD) or a level-sensitive latch (LD). The storage-element pair on either the Output path or the Three-State path can be used together with a special multiplexer to produce Double-Data-Rate (DDR) transmission.
This is accomplished by taking data synchronized to the clock signal's rising edge and converting it to bits synchronized on both the rising and the falling edge. The combination of two registers and a multiplexer is referred to as a Double-Data-Rate D-type flip-flop (ODDR2). Table 1 describes the signal paths associated with the storage element.
Table 1: Storage Element Signal Description
Storage Element Signal D Q CK CE SR
Description Data input Data output Clock input Clock Enable input Set/Reset input
Function Data at this input is stored on the active edge of CK and enabled by CE. For latch operation when the input is enabled, data passes directly to the output Q. The data on this output reflects the state of the storage element. For operation as a latch in transparent mode, Q mirrors the data at D. Data is loaded into the storage element on this input's active edge with CE asserted. When asserted, this input enables CK. If not connected, CE defaults to the asserted state. This input forces the storage element into the state specified by the SRHIGH/SRLOW attributes. The SYNC/ASYNC attribute setting determines if the SR input is synchronized to the clock or not. If both SR and REV are active at the same time, the storage element gets a value of 0. This input is used together with SR. It forces the storage element into the state opposite from what SR does. The SYNC/ASYNC attribute setting determines whether the REV input is synchronized to the clock or not. If both SR and REV are active at the same time, the storage element gets a value of 0. trols the CE inputs for the register pair on the three-state path and ICE does the same for the register pair on the input path. The Set/Reset (SR) line entering the IOB controls all six registers, as is the Reverse (REV) line. In addition to the signal polarity controls described in IOB Overview, each storage element additionally supports the controls described in Table 2.
REV
Reverse input
As shown in Figure 1, the upper registers in both the output and three-state paths share a common clock. The OTCLK1 clock signal drives the CK clock inputs of the upper registers on the output and three-state paths. Similarly, OTCLK2 drives the CK inputs for the lower registers on the output and three-state paths. The upper and lower registers on the input path have independent clock lines: ICLK1 and ICLK2. The OCE enable line controls the CE inputs of the upper and lower registers on the output path. Similarly, TCE con-
Table 2: Storage Element Options
Option Switch FF/Latch SYNC/ASYNC Function Chooses between an edge-triggered flip-flop or a level-sensitive latch Determines whether the SR set/reset control is synchronous or asynchronous Specificity Independent for each storage element Independent for each storage element
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Functional Description
Table 2: Storage Element Options
Option Switch SRHIGH/SRLOW Function Determines whether SR acts as a Set, which forces the storage element to a logic "1" (SRHIGH) or a Reset, which forces a logic "0" (SRLOW) When Global Set/Reset (GSR) is asserted or after configuration this option specifies the initial state of the storage element, either set (INIT1) or reset (INIT0). By default, choosing SRLOW also selects INIT0; choosing SRHIGH also selects INIT1. Specificity Independent for each storage element, except when using ODDR2. In the latter case, the selection for the upper element will apply to both elements. Independent for each storage element, except when using ODDR2, which uses two IOBs. In the ODDR2 case, selecting INIT0 for one IOBs applies to both elements within the IOB, although INIT1 could be selected for the elements in the other IOB.
INIT1/INIT0
Double-Data-Rate Transmission
Double-Data-Rate (DDR) transmission describes the technique of synchronizing signals to both the rising and falling edges of the clock signal. Spartan-3E devices use register pairs in all three IOB paths to perform DDR operations. The pair of storage elements on the IOB's Output path (OFF1 and OFF2), used as registers, combine with a special multiplexer to form a DDR D-type flip-flop (ODDR2). This primitive permits DDR transmission where output data bits are synchronized to both the rising and falling edges of a clock. DDR operation requires two clock signals (usually 50% duty cycle), one the inverted form of the other. These signals trigger the two registers in alternating fashion, as shown in Figure 3. The Digital Clock Manager (DCM) generates the two clock signals by mirroring an incoming signal, and then shifting it 180 degrees. This approach ensures minimal skew between the two signals. Alternatively, the inverter inside the IOB can be used to invert the clock signal, thus only using one clock line and both rising and falling edges of that clock line as the two clocks for the DDR flip-flops.
DCM 180 0 FDDR D1 Q1 CLK1 DDR MUX D2 Q2 CLK2
Q
The storage-element pair on the Three-State path (TFF1 and TFF2) also can be combined with a local multiplexer to form a DDR primitive. This permits synchronizing the output enable to both the rising and falling edges of a clock. This DDR operation is realized in the same way as for the output path. The storage-element pair on the input path (IFF1 and IFF2) allows an I/O to receive a DDR signal. An incoming DDR clock signal triggers one register, and the inverted clock signal triggers the other register. The registers take turns capturing bits of the incoming DDR data signal. The primitive to allow this functionality is called IDDR2. Aside from high bandwidth data transfers, DDR outputs also can be used to reproduce, or mirror, a clock signal on the output. This approach is used to transmit clock and data signals together (source synchronously). A similar approach is used to reproduce a clock signal at multiple outputs. The advantage for both approaches is that skew across the outputs is minimal.
DCM 0 FDDR D1 Q1 CLK1 DDR MUX D2 Q2 CLK2
Q
DS312-2_20_021105
Figure 3: Two Methods for Clocking the DDR Register
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Register Cascade Feature
In the Spartan-3E family, one of the IOBs in a differential pair can cascade either its input or output storage elements with those in the other IOB of the differential pair. This is intended to make DDR operation at high speed much simpler to implement. The new DDR connections that are available are shown in Figure 1 (dashed lines), and are only available for routing between IOBs and are not accessible to the FPGA fabric. Note that this feature is only available when using differential I/O.
D PAD To Fabric Q IQ2 IDDRIN2 D Q D2 Q D1
D
ICLK1
IDDR2
As a DDR input pair, the master IOB registers incoming data on the rising edge of ICLK1 (= D1) and the rising edge of ICLK2 (= D2), which is typically the same as the falling edge of ICLK1. This data is then transferred into the FPGA fabric. At some point, both signals must be brought into the same clock domain, typically ICLK1. This can be difficult at high frequencies because the available time is only one half of a clock cycle assuming a 50% duty cycle. See Figure 4 for a graphical illustration of this function. In the Spartan-3E device, the signal D2 can be cascaded into the storage element of the adjacent slave IOB. There it is re-registered to ICLK1, and only then fed to the FPGA fabric where it is now already in the same time domain as D1. Here, the FPGA fabric uses only the clock ICLK1 to process the received data. See Figure 5 for a graphical illustration of this function.
ICLK2
ICLK1 ICLK2 PAD D1 D2 d d+1 d d-1 d+2 d+3 d+2 d+1 d+4 d+5 d+4 d+3 d+6 d+7 d+6 d+5 d+8 d+8 d+7
DS312-2_22_030105
Figure 5: Input DDR Using Spartan-3E Cascade Feature
ODDR2
As a DDR output pair, the master IOB registers data coming from the FPGA fabric on the rising edge of OCLK1 (= D1) and the rising edge of OCLK2 (= D2), which is typically the same as the falling edge of OCLK1. These two bits of data are multiplexed by the DDR mux and forwarded to the output pin. At some point in the FPGA fabric, the signal D2 must be brought into the clock domain OCLK2 from the domain OCLK1. This can be difficult at high frequencies, because the time available is only one half a clock cycle. See Figure 6 for a graphical illustration of this function. In the Spartan-3E device, the signal D2 can be cascaded via the storage element of the adjacent slave IOB. Here, it is registered by OCLK1 and then forwarded to the master IOB where it is re-registered to OCLK2, selected as usual by the DDR multiplexer, and then forwarded to the output pin. This way the data for transmission can be processed using just the clock OCLK1 in the FPGA fabric. See Figure 7 for a graphical illustration of this function.
D PAD
Q
D1 To Fabric
D
Q
D2
ICLK2 ICLK1 ICLK1 ICLK2 PAD D1 D2 d-1 d d+1 d+2 d+3 d+4 d+5 d d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8 d+6 d+8 d+7
DS312-2_21_021105
Figure 4: Input DDR (without Cascade Feature)
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D1 From Fabric D2
D
Q PAD
D1 From Fabric
D
Q PAD
D
Q
D2
ODDROUT1
D
Q
ODDRIN2
D
Q
OCLK1 OCLK2
OCLK1 OCLK2
OCLK1 OCLK2 D1 D2 PAD d d+1 d d+2 d+3 d+1 d+2 d+4 d+5 d+3 d+4 d+6 d+7 d+5 d+6 d+8 d+10 d+9 d+7 d+8
OCLK1 OCLK2 D1 d d+2 d+3 d d+1 d+4 d+5 d+2 d+3 d+6 d+7 d+4 d+5 d+8 d+9 d+6 d+7 d+8
D2 d+1 PAD
DS312-2_23_030105
DS312-2_36_030105
Figure 6: Output DDR (without Cascade Feature)
Figure 7: Output DDR Using Spartan-3E Cascade Feature
SelectIO Signal Standards
The Spartan-3E I/Os feature inputs and outputs that support a wide range of I/O signaling standards (Table 3 and Table 4). The majority of the I/Os also can be used to form differential pairs to support any of the differential signaling standards (Table 4). To define the I/O signaling standard in a design, set the IOSTANDARD attribute to the appropriate setting. Xilinx provides a variety of different methods for applying the IOSTANDARD for maximum flexibility. For a full description of different methods of applying attributes to control IOSTANDARD, refer to "Entry Strategies for Xilinx Constraints" in the Xilinx Software Manuals and Help. Spartan-3E FPGAs provide additional input flexibility by allowing I/O standards to be mixed in different banks. Special care must be taken to ensure the input voltages do not exceed VCCO (see Module 3 for the specifications). For a particular VCCO voltage, Table 3 and Table 4 list all of the IOSTANDARDs that can be combined and if the IOSTANDARD is supported as an input only or can be used for both inputs and outputs.
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Functional Description
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Table 3: Single-Ended IOSTANDARD Bank Compatibility
VCCO Supply/Compatibility
Single-Ended IOSTANDARD
Input Requirements VREF for Inputs N/R N/R N/R N/R N/R N/R(1) N/R N/R N/R 0.9 1.1 0.9 1.25 Board Termination Voltage (VTT) N/R N/R N/R N/R N/R N/R N/R N/R N/R 0.9 1.8 0.9 1.25
1.2 V Input/ Output -
1.5 V Input/ Output Input -
1.8 V Input/ Output Input Input -
2.5 V Input/ Output Input Input Input -
3.0 V Input Input Input Input Input/ Output Input/ Output Input/ Output
3.3 V Input/ Output Input/ Output Input Input Input Input Input Input Input Input Input Input Input
LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3 PCI66_3 PCIX HSTL_I_18 HSTL_III_18 SSTL18_I SSTL2_I
Notes:
1.
-
-
Input/ Output Input/ Output Input/ Output -
Input Input Input Input/ Output
Input Input Input Input
N/R - Not required for input operation.
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Functional Description
Table 4: Differential IOSTANDARD Bank Compatibility
Differential IOSTANDARD LVDS_25 VCCO Supply 2.5V Input, On-chip Differential Termination, Output(1) Input, On-chip Differential Termination, Output(1) Input, On-chip Differential Termination, Output(1) Input, On-chip Differential Termination Input, On-chip Differential Termination, Output 3.3V Input Input Requirements: VREF
RSDS_25
Input N/R Input (Not Required)
MINI_LVDS_25
LVPECL_25
Input
BLVDS_25 Notes:
1.
Input
Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs.
HSTL and SSTL inputs use the Reference Voltage (VREF) to bias the input-switching threshold. Once a configuration data file is loaded into the FPGA that calls for the I/Os of a given bank to use HSTL/SSTL, a few specifically reserved I/O pins on the same bank automatically convert to VREF inputs. For banks that do not contain HSTL or SSTL, VREF pins remain available for user I/Os or input pins. Differential standards employ a pair of signals, one the opposite polarity of the other. The noise canceling properties (for example, Common-Mode Rejection) of these standards permit exceptionally high data transfer rates. This subsection introduces the differential signaling capabilities of Spartan-3E devices. Each device-package combination designates specific I/O pairs specially optimized to support differential standards. Differential pairs can be shown in the Pin and Area Constraints Editor (PACE) with the "Show Differential Pairs" option. A unique L-number, part of the pin name, identifies the line-pairs associated with each bank (see Module 4). For each pair, the letters P and N designate the true and inverted lines, respectively. For example, the pin names IO_L43P_3 and IO_L43N_3 indicate the true and inverted lines comprising the line pair L43 on Bank 3. VCCO provides current to the outputs and additionally powers the On-Chip Differential Termination. VCCO must be 2.5V when using the On-Chip Differential Termination. The VREF lines are not required for differential operation. To further understand how to combine multiple IOSTANDARDs within a bank, refer to IOBs Organized into Banks, page 10.
(See Module 3 for the specific range). The on-chip input differential termination in Spartan-3E devices eliminates the external 100 termination resistor commonly found in differential receiver circuits. Use differential termination for LVDS, mini-LVDS, and BLVDS as applications permit. On-chip Differential Termination is available in banks with VCCO = 2.5V and is not supported on dedicated input pins. Set the DIFF_TERM attribute to TRUE to enable Differential Termination on a differential I/O pin pair. The DIFF_TERM attribute uses the following syntax in the UCF file:
INST DIFF_TERM = "";
Z0 = 50 Spartan-3E Differential Input with On-Chip Differential Terminator
Z0 = 50
DS312-2_24_021505
Figure 8: Differential Inputs and Outputs
On-Chip Differential Termination
Spartan-3E devices provide an on-chip 100 differential termination across the input differential receiver terminals
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Pull-Up and Pull-Down Resistors
Pull-up and pull-down resistors inside each IOB optionally force a floating I/O pin to a determined state. Pull-up and
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100
Spartan-3E Differential Output
Z0 = 50
100
Spartan-3E Differential Output
Z0 = 50
Spartan-3E Differential Input
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Functional Description pull-down resistors are commonly applied to unused I/Os, inputs, and three-state outputs, but can be used on any I/O. The pull-up resistor connects an I/O to VCCO through a resistor. The resistance value depends on the VCCO voltage (see Module 3 for the specifications). The pull-down resistor similarly connects an I/O to ground with a resistor. The PULLUP and PULLDOWN attributes and library primitives turn on these optional resistors. By default, PULLDOWN resistors terminate all unused I/Os. Unused I/Os can alternatively be set to PULLUP or FLOAT. To change the unused I/O Pad setting, set the Bitstream Generator (BitGen) option UnusedPin to PULLUP, PULLDOWN, or FLOAT. The UnusedPin option is accessed through the Properties for Generate Programming File in ISE. During configuration a Low logic level on HSWAP activates the pull-up resistors for all I/Os not used directly in the selected configuration mode.
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To adjust the drive strength for each output set the DRIVE attribute to the desired drive strength: 2, 4, 6, 8, 12, and 16.
Table 5: Programmable Output Drive Current
Signal Standard LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 Output Drive Current (mA) 2 4 6 8 12 16
Keeper Circuit
Each I/O has an optional keeper circuit (see Figure 9) that keeps bus lines from floating when not being actively driven. The KEEPER circuit retains the last logic level on a line after all drivers have been turned off. Apply the KEEPER attribute or use the KEEPER library primitive to use the KEEPER circuitry. Pull-up and pull-down resistors override the KEEPER settings.
Weak Pull-up
High output current drive strength and FAST output slew rates generally result in fastest I/O performance. However, these same settings generally also result in transmission line effects on the printed circuit board (PCB) for all but the shortest board traces. Each IOB has independent slew rate and drive strength controls. Use the slowest slew rate and lowest output drive current that meets the performance requirements for the end application. Likewise, due to lead inductance, a given package supports a limited number of simultaneous switching outputs (SSOs) when using fast, high-drive outputs. Only use fast, high-drive outputs when required by the application.
IOBs Organized into Banks
Output Path Input Path Keeper Weak Pull-down
DS312-2_25_022805
The Spartan-3E architecture organizes IOBs into four I/O banks as shown in Figure 10. Each bank maintains separate VCCO and VREF supplies. The separate supplies allow each bank to independently set VCCO. Similarly, the VREF supplies may be set for each bank. Refer to Table 3 and Table 4 for VCCO and VREF requirements. When working with Spartan-3E devices, most of the differential I/O standards are compatible and can be combined within any given bank. Each bank can support any two of the following differential standards: LVDS_25 outputs, MINI_LVDS_25 outputs, and RSDS_25 outputs. As an example, LVDS_25 outputs, RSDS_25 outputs, and any other differential inputs while using on-chip differential termination are a valid combination. A combination not allowed is a single bank with LVDS_25 outputs, RSDS_25 outputs, and MINI_LVDS_25 outputs.
Figure 9: Keeper Circuit
Slew Rate Control and Drive Strength
Each IOB has a slew-rate control that sets the output switching edge-rate for LVCMOS and LVTTL outputs. The SLEW attribute controls the slew rate and can either be set to SLOW (default) or FAST. Each LVCMOS and LVTTL output additionally supports up to six different drive current strengths as shown in Table 5.
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Functional Description are outlined for each package, such as pins that are unconnected on one device but connected on another in the same package or pins that are dedicated inputs on one package but full I/O on another. When designing the printed circuit board (PCB), plan for potential future upgrades and package migration. The Spartan-3E family is not pin-compatible with any previous Xilinx FPGA family.
Bank 0
Bank 3
Bank 1
Dedicated Inputs
Bank 2
DS312-2_26_021205
Figure 10: Spartan-3E I/O Banks (top view)
I/O Banking Rules
When assigning I/Os to banks, these VCCO rules must be followed: 1. All VCCO pins on the FPGA must be connected even if a bank is unused. 2. All VCCO lines associated within a bank must be set to the same voltage level. 3. The VCCO levels used by all standards assigned to the I/Os of any given bank must agree. The Xilinx development software checks for this. Table 3 and Table 4 describe how different standards use the VCCO supply. 4. If a bank does not have any VCCO requirements, connect VCCO to an available voltage, such as 2.5V or 3.3V. Some configuration modes might place additional VCCO requirements. Refer to Configuration, page 56 for more information. If any of the standards assigned to the Inputs of the bank use VREF, then the following additional rules must be observed: 1. All VREF pins must be connected within a bank. 2. All VREF lines associated with the bank must be set to the same voltage level. 3. The VREF levels used by all standards assigned to the Inputs of the bank must agree. The Xilinx development software checks for this. Table 3 describes how different standards use the VREF supply. If VREF is not required to bias the input switching thresholds, all associated VREF pins within the bank can be used as user I/Os or input pins.
Dedicated Inputs are IOBs used only as inputs. Pin names designate a Dedicated Input if the name starts with IP, for example, IP or IP_Lxxx_x. Dedicated inputs retain the full functionality of the IOB for input functions with a single exception for differential inputs (IP_Lxxx_x). For the differential Dedicated Inputs, the on-chip differential termination is not available. To replace the on-chip differential termination, choose a differential pair that supports outputs (IO_Lxxx_x) or use an external 100 termination resistor on the board.
ESD Protection
Clamp diodes protect all device pads against damage from Electro-Static Discharge (ESD) as well as excessive voltage transients. Each I/O has two clamp diodes: one diode extends P-to-N from the pad to VCCO and a second diode extends N-to-P from the pad to GND. During operation, these diodes are normally biased in the off state. These clamp diodes are always connected to the pad, regardless of the signal standard selected. The presence of diodes limits the ability of Spartan-3E I/Os to tolerate high signal voltages. The VIN absolute maximum rating in Table 1 of Module 3 specifies the voltage range that I/Os can tolerate.
Supply Voltages for the IOBs
The IOBs are powered by three supplies: 1. The VCCO supplies, one for each of the FPGA's I/O banks, power the output drivers. The voltage on the VCCO pins determines the voltage swing of the output signal. 2. VCCINT is the main power supply for the FPGA's internal logic. 3. VCCAUX is an auxiliary source of power, primarily to optimize the performance of various FPGA functions such as I/O switching.
Package Footprint Compatibility
Sometimes, applications outgrow the logic capacity of a specific Spartan-3E FPGA. Fortunately, the Spartan-3E family is designed so that multiple part types are available in pin-compatible package footprints, as described in Module 4. In some cases, there are subtle differences between devices available in the same footprint. These differences
The I/Os During Power-On, Configuration, and User Mode
All I/Os have ESD clamp diodes to their respective VCCO supply and from GND, as shown in Figure 1. The VCCINT (1.2V), VCCAUX (2.5V), and VCCO supplies can be applied in any order. Before the FPGA can start its configuration process, VCCINT, VCCO Bank 2, and VCCAUX must have reached their respective minimum recommended operating
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Functional Description levels (see Table 2 of Module 3). At this time, all I/O drivers are in a high-impedance state. VCCO Bank 2, VCCINT, and VCCAUX serve as inputs to the internal Power-On Reset circuit (POR). A Low level applied to the HSWAP input enables pull-up resistors on User I/Os from power-on throughout configuration. A High level on HSWAP disables the pull-up resistors, allowing the I/Os to float. HSWAP contains a weak pull-up and defaults to High if left floating. As soon as power is applied, the FPGA begins initializing its configuration memory. At the same time, the FPGA internally asserts the Global Set-Reset (GSR), which asynchronously resets all IOB storage elements to a default Low state. Upon the completion of initialization and the beginning of configuration, INIT_B goes High, sampling the M0, M1, and M2 inputs to determine the configuration mode. At this point in time, the configuration data is loaded into the FPGA. The I/O drivers remain in a high-impedance state (with or without pull-up resistors, as determined by the HSWAP input) throughout configuration. At the end of configuration, the GSR net is released, placing the IOB registers in a Low state by default, unless the
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loaded design reverses the polarity of their respective SR inputs. The Global Three State (GTS) net is released during Start-Up, marking the end of configuration and the beginning of design operation in the User mode. After the GTS net is released, all user I/Os go active while all unused I/Os are weakly pulled down (PULLDOWN). The designer can control how the unused I/Os are terminated after GTS is released by setting the Bitstream Generator (BitGen) option UnusedPin to PULLUP, PULLDOWN, or FLOAT. One clock cycle later (default), the Global Write Enable (GWE) net is released allowing the RAM and registers to change states. Once in User mode, any pull-up resistors enabled by HSWAP revert to the user settings and HSWAP is available as a general-purpose I/O. For more information on PULLUP and PULLDOWN, see Pull-Up and Pull-Down Resistors.
JTAG Boundary-Scan Capability
All Spartan-3E IOBs support boundary-scan testing compatible with IEEE 1149.1/1532 standards. See JTAG Mode, page 86 for more information on programming via JTAG.
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Functional Description and additional multiplexers and carry logic simplify wide logic and arithmetic functions. Most general-purpose logic in a design is automatically mapped to the slice resources in the CLBs. Each CLB is identical, and the Spartan-3E family CLB structure is identical to that for the Spartan-3 family.
Configurable Logic Block (CLB) and Slice Resources
CLB Overview
The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as combinatorial circuits. Each CLB contains four slices, and each slice contains two Look-Up Tables (LUTs) to implement logic and two dedicated storage elements that can be used as flip-flops or latches. The LUTs can be used as a 16x1 memory (RAM16) or as a 16-bit shift register (SRL16),
CLB Array
The CLBs are arranged in a regular array of rows and columns as shown in Figure 11. Each density varies by the number of rows and columns of CLBs (see Table 6).
X0Y3 X0Y2
X1Y3 X1Y2
X2Y3 X2Y2
X3Y3 X3Y2
Spartan-3E FPGA
X0Y1 X0Y0
X1Y1 X1Y0
X2Y1 X2Y0 IOBs
X3Y1 X3Y0
CLB
Slice
DS312-2_31_021205
Figure 11: CLB Locations
Table 6: Spartan-3E CLB Resources
Device XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E
Notes:
1. The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are embedded in the array (see Module 1, Figure 1).
CLB Rows 22 34 46 60 76
CLB Columns 16 26 34 46 58
CLB Total(1) 240 612 1164 2168 3688
Slices 960 2448 4656 8672 14752
LUTs / Flip-Flops 1920 4896 9312 17344 29504
Equivalent Logic Cells 2160 5508 10476 19512 33192
RAM16 / SRL16 960 2448 4656 8672 14752
Distributed RAM Bits 15360 39168 74496 138752 236032
Slices
Each CLB comprises four interconnected slices, as shown in Figure 13. These slices are grouped in pairs. Each pair is organized as a column with an independent carry chain. The left pair supports both logic and memory functions and its slices are called SLICEM. The right pair supports logic only and its slices are called SLICEL. Therefore half the
LUTs support both logic and memory (including both RAM16 and SRL16 shift registers) while half support logic only, and the two types alternate throughout the array columns. The SLICEL reduces the size of the CLB and lowers the cost of the device, and can also provide a performance advantage over the SLICEM.
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Functional Description
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WF[4:1]
DS312-2_32_021205
Notes:
1. 2. Options to invert signal polarity as well as other options that enable lines for various functions are not shown. The index i can be 6, 7, or 8, depending on the slice. The upper SLICEL has an F8MUX, and the upper SLICEM has an F7MUX. The lower SLICEL and SLICEM both have an F6MUX.
Figure 12: Simplified Diagram of the Left-Hand SLICEM
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Functional Description
Left-Hand SLICEM (Logic or Distributed RAM or Shift Register)
Right-Hand SLICEL (Logic Only) COUT
CLB SLICE X1Y1
SLICE X1Y0 Switch Matrix COUT CIN SLICE X0Y1 SHIFTOUT SHIFTIN SLICE X0Y0 Interconnect to Neighbors
CIN
DS099-2_05_082104
Figure 13: Arrangement of Slices within the CLB
Slice Location Designations
The Xilinx development software designates the location of a slice according to its X and Y coordinates, starting in the bottom left corner, as shown in Figure 11. The letter 'X' followed by a number identifies columns of slices, incrementing from the left side of the die to the right. The letter 'Y' followed by a number identifies the position of each slice in a pair as well as indicating the CLB row, incrementing from the bottom of the die. Figure 13 shows the CLB located in the lower left-hand corner of the die. The SLICEM always has an even 'X' number, and the SLICEL always has an odd 'X' number.
Slice Overview
A slice includes two LUT function generators and two storage elements, along with additional logic, as shown in Figure 14. Both SLICEM and SLICEL have the following elements in common to provide logic, arithmetic, and ROM functions: * * * * Two 4-input LUT function generators, F and G Two storage elements Two wide-function multiplexers, F5MUX and FiMUX Carry and arithmetic logic
SRL16 RAM16 LUT4 (G)
FiMUX Carry Register
LUT4 (G)
FiMUX Carry Register
F5MUX
SRL16 RAM16 LUT4 (F)
F5MUX Register
LUT4 (F)
Carry
Carry
Register
Arithmetic Logic
Arithmetic Logic
SLICEM
SLICEL
DS312-2_13_020905
Figure 14: Resources in a Slice
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Functional Description The SLICEM pair supports two additional functions: * * Two 16x1 distributed RAM blocks, RAM16 Two 16-bit shift registers, SRL16
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Enable (CE), Slice Write Enable (SLICEWE1), and Reset/Set (RS) are shared in common between the two halves. The LUTs located in the top and bottom portions of the slice are referred to as "G" and "F", respectively, or the "G-LUT" and the "F-LUT". The storage elements in the top and bottom portions of the slice are called FFY and FFX, respectively. Each slice has two multiplexers with F5MUX in the bottom portion of the slice and FiMUX in the top portion. Depending on the slice, the FiMUX takes on the name F6MUX, F7MUX, or F8MUX, according to its position in the multiplexer chain. The lower SLICEL and SLICEM both have an F6MUX. The upper SLICEM has an F7MUX, and the upper SLICEL has an F8MUX. The carry chain enters the bottom of the slice as CIN and exits at the top as COUT. Five multiplexers control the chain: CYINIT, CY0F, and CYMUXF in the bottom portion and CY0G and CYMUXG in the top portion. The dedicated arithmetic logic includes the exclusive-OR gates XORF and XORG (bottom and top portions of the slice, respectively) as well as the AND gates FAND and GAND (bottom and top portions, respectively). See Table 7 for a description of all the slice input and output signals.
Each of these elements is described in more detail in the following sections.
Logic Cells
The combination of a LUT and a storage element is known as a "Logic Cell". The additional features in a slice, such as the wide multiplexers, carry logic, and arithmetic gates, add to the capacity of a slice, implementing logic that would otherwise require additional LUTs. Benchmarks have shown that the overall slice is equivalent to 2.25 simple logic cells. This calculation provides the equivalent logic cell count shown in Table 6.
Slice Details
Figure 16 is a detailed diagram of the SLICEM. It represents a superset of the elements and connections to be found in all slices. The dashed and gray lines (blue when viewed in color) indicate the resources found only in the SLICEM and not in the SLICEL. Each slice has two halves, which are differentiated as top and bottom to keep them distinct from the upper and lower slices in a CLB. The control inputs for the clock (CLK), Clock
Table 7: Slice Inputs and Outputs
Name F[4:1] G[4:1] BX BY BXOUT BYOUT ALTDIG DIG SLICEWE1 F5 FXINA FXINB Fi CE SR Location SLICEL/M Bottom SLICEL/M Top SLICEL/M Bottom SLICEL/M Top SLICEM Bottom SLICEM Top SLICEM Top SLICEM Top SLICEM Common SLICEL/M Bottom SLICEL/M Top SLICEL/M Top SLICEL/M Top SLICEL/M Common SLICEL/M Common Direction Input Input Input Input Output Output Input Output Input Output Input Input Output Input Input F-LUT and FAND inputs G-LUT and GAND inputs or Write Address (SLICEM) Bypass to or output (SLICEM) or storage element, or control input to F5MUX, input to carry logic, or data input to RAM (SLICEM) Bypass to or output (SLICEM) or storage element, or control input to FiMUX, input to carry logic, or data input to RAM (SLICEM) BX bypass output BY bypass output Alternate data input to RAM ALTDIG or SHIFTIN bypass output RAM Write Enable Output from F5MUX; direct feedback to FiMUX Input to FiMUX; direct feedback from F5MUX or another FiMUX Input to FiMUX; direct feedback from F5MUX or another FiMUX Output from FiMUX; direct feedback to another FiMUX FFX/Y Clock Enable FFX/Y Set or Reset or RAM Write Enable (SLICEM) Description
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Table 7: Slice Inputs and Outputs (Continued)
Name CLK SHIFTIN SHIFTOUT CIN COUT X Y XB YB XQ YQ Location SLICEL/M Common SLICEM Top SLICEM Bottom SLICEL/M Bottom SLICEL/M Top SLICEL/M Bottom SLICEL/M Top SLICEL/M Bottom SLICEL/M Top SLICEL/M Bottom SLICEL/M Top Direction Input Input Output Input Output Output Output Output Output Output Output Description FFX/Y Clock or RAM Clock (SLICEM) Data input to G-LUT RAM Shift data output from F-LUT RAM Carry chain input Carry chain output Combinatorial output Combinatorial output Combinatorial output from carry or F-LUT SRL16 (SLICEM) Combinatorial output from carry or G-LUT SRL16 (SLICEM) FFX output FFY output BY in the top half) can take any of several possible branches: 1. Bypass both the LUT and the storage element, and then exit the slice as BXOUT (or BYOUT) and return to interconnect. 2. Bypass the LUT, and then pass through a storage element via the D input before exiting as XQ (or YQ). 3. Control the wide function multiplexer F5MUX (or FiMUX). 4. Via multiplexers, serve as an input to the carry chain. 5. Drive the DI input of the LUT. 6. BY can control the REV inputs of both the FFY and FFX storage elements. See Storage Element Functions. 7. Finally, the DIG_MUX multiplexer can switch BY onto the DIG line, which exits the slice. The control inputs CLK, CE, SR, BX and BY have programmable polarity. The LUT inputs do not need programmable polarity because their function can be inverted inside the LUT. The sections that follow provide more detail on individual functions of the slice.
Main Logic Paths
Central to the operation of each slice are two nearly identical data paths at the top and bottom of the slice. The description that follows uses names associated with the bottom path. (The top path names appear in parentheses.) The basic path originates at an interconnect switch matrix outside the CLB. See Interconnect for more information on the switch matrix and the routing connections. Four lines, F1 through F4 (or G1 through G4 on the upper path), enter the slice and connect directly to the LUT. Once inside the slice, the lower 4-bit path passes through a LUT "F" (or "G") that performs logic operations. The LUT Data output, "D", offers five possible paths: 1. Exit the slice via line "X" (or "Y") and return to interconnect. 2. Inside the slice, "X" (or "Y") serves as an input to the DXMUX (or DYMUX) which feeds the data input, "D", of the FFY (or FFX) storage element. The "Q" output of the storage element drives the line XQ (or YQ) which exits the slice. 3. Control the CYMUXF (or CYMUXG) multiplexer on the carry chain. 4. With the carry chain, serve as an input to the XORF (or XORG) exclusive-OR gate that performs arithmetic operations, producing a result on "X" (or "Y"). 5. Drive the multiplexer F5MUX to implement logic functions wider than four bits. The "D" outputs of both the F-LUT and G-LUT serve as data inputs to this multiplexer. In addition to the main logic paths described above, there are two bypass paths that enter the slice as BX and BY. Once inside the FPGA, BX in the bottom half of the slice (or
Look-Up Tables
The Look-Up Table or LUT is a RAM-based function generator and is the main resource for implementing logic functions. Furthermore, the LUTs in each SLICEM pair can be configured as Distributed RAM or a 16-bit shift register, as described later. Each of the two LUTs (F and G) in a slice have four logic inputs (A1-A4) and a single output (D). Any four-variable Boolean logic operation can be implemented in one LUT. Functions with more inputs can be implemented by cascad17
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Functional Description ing LUTs or by using the wide function multiplexers that are described later. The output of the LUT can connect to the wide multiplexer logic, the carry and arithmetic logic, or directly to a CLB output or to the CLB storage element. See Figure 15.
Y
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Wide Multiplexers
Wide-function multiplexers effectively combine LUTs in order to permit more complex logic operations. Each slice has two of these multiplexers with F5MUX in the bottom portion of the slice and FiMUX in the top portion. The F5MUX multiplexes the two LUTs in a slice. The FiMUX multiplexes two CLB inputs which connect directly to the F5MUX and FiMUX results from the same slice or from other slices. See Figure 16.
G[4:1]
A[4:1] G-LUT
D FFY
YQ
X 4 F[4:1] A[4:1] F-LUT D FFX XQ
DS312-2_33_022205
Figure 15: LUT Resources in a Slice
FiMUX FXINA FXINB BY DQ F5MUX F[4:1] G[4:1] BX DQ LUT LUT 1 F5 (Local Feedback to FXIN) 0 X (General Interconnect) XQ 1 FX (Local Feedback to FXIN) 0 Y (General Interconnect) YQ
x312-2_34_021205
Figure 16: Dedicated Multiplexers in Spartan-3E CLB
Depending on the slice, FiMUX takes on the name F6MUX, F7MUX, or F8MUX. The designation indicates the number of inputs possible without restriction on the function. For example, an F7MUX can generate any function of seven inputs. Figure 17 shows the names of the multiplexers in each position in the Spartan-3E CLB. The figure also includes the direct connections within the CLB, along with the F7MUX connection to the CLB below. Each mux can create logic functions of more inputs than indicated by its name. The F5MUX, for example, can generate any function of five inputs, with four inputs duplicated to two LUTs and the fifth input controlling the mux. Because each LUT can implement independent 2:1 muxes, the F5MUX can combine them to create a 4:1 mux, which is a six-input function. If the two LUTs have completely independent sets of inputs, some functions of all nine inputs can be implemented. Table 8 shows the connections for each multiplexer and the number of inputs possible for different types of functions.
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Functional Description
FXINB F8 FXINA X
F5
F5
FXINB F6 FXINA
FX
F5
F5
FXINB FXINA F7
FX
F5
F5
FXINB FXINA F6 FX
F5
F5
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Figure 17: Muxes and Dedicated Feedback in Spartan-3E CLB Table 8: Mux Capabilities
Total Number of Inputs per Function Mux F5MUX FiMUX Usage F5MUX F6MUX F7MUX F8MUX Input Source LUTs F5MUX F6MUX F7MUX For Any Function 5 6 7 8 For Mux 6 (4:1 mux) 11 (8:1 mux) 20 (16:1 mux) 37 (32:1 mux) For Limited Functions 9 19 39 79
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Functional Description The wide multiplexers can be used by the automatic tools or instantiated in a design using a component such as the F5MUX. The symbol, signals, and function are described below. The description is similar for the F6MUX, F7MUX, and F8MUX. Each has versions with a general output, local output, or both.
I0 I1 S
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Table 10: F5MUX Function
Inputs S 0 0 I0 1 0 X X I1 X X 1 0 O 1 0 1 0 Outputs LO 1 0 1 0
0 1
LO O
1 1
Figure 18: F5MUX with Local and General Outputs Table 9: F5MUX Inputs and Outputs
Signal I0 I1 S LO Function Input selected when S is Low Input selected when S is High Select input Local Output that connects to the F5 or FX CLB pins, which use local feedback to the FXIN inputs to the FiMUX for cascading General Output that connects to the general-purpose combinatorial or registered outputs of the CLB
For more details on using the multiplexers, see XAPP466: "Using Dedicated Multiplexers in Spartan-3 FPGAs".
Carry and Arithmetic Logic
The carry chain, together with various dedicated arithmetic logic gates, support fast and efficient implementations of math operations. The carry logic is automatically used for most arithmetic functions in a design. The gates and multiplexers of the carry and arithmetic logic can also be used for general-purpose logic, including simple wide Boolean functions. The carry chain enters the slice as CIN and exits as COUT, controlled by several multiplexers. The carry chain connects directly from one CLB to the CLB above. The carry chain can be initialized at any point from the BX (or BY) inputs. The dedicated arithmetic logic includes the exclusive-OR gates XORF and XORG (upper and lower portions of the slice, respectively) as well as the AND gates GAND and FAND (upper and lower portions, respectively). These gates work in conjunction with the LUTs to implement efficient arithmetic functions, including counters and multipliers, typically at two bits per slice. See Figure 19 and Table 11.
O
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COUT
YB 1 G[4:1] G1 G2 A[4:1] G-LUT D XORG CY0G FFY YQ CYMUXG CYSELG Y
GAND BY
1 0
XB 1 4 F[4:1] F1 F2 A[4:1] F-LUT D XORF CY0F FFX XQ CYSELF CYMUXF X
FAND BX
1 0
CYINIT
CIN
DS312-2_14_021305
Figure 19: Carry Logic Table 11: Carry Logic Functions
Function CYINIT Description Initializes carry chain for a slice. Fixed selection of: * CIN carry input from the slice below * BX input Carry generation for bottom half of slice. Fixed selection of: * F1 or F2 inputs to the LUT (both equal 1 when a carry is to be generated) * FAND gate for multiplication * BX input for carry initialization * Fixed "1" or "0" input for use as a simple Boolean function Carry generation for top half of slice. Fixed selection of: * G1 or G2 inputs to the LUT (both equal 1 when a carry is to be generated) * GAND gate for multiplication * BY input for carry initialization * Fixed "1" or "0" input for use as a simple Boolean function Carry generation or propagation mux for bottom half of slice. Dynamic selection via CYSELF of: * CYINIT carry propagation (CYSELF = 1) * CY0F carry generation (CYSELF = 0)
CY0F
CY0G
CYMUXF
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Functional Description
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Table 11: Carry Logic Functions (Continued)
Function CYMUXG Description Carry generation or propagation mux for top half of slice. Dynamic selection via CYSELF of: * CYMUXF carry propagation (CYSELG = 1) * CY0G carry generation (CYSELG = 0) Carry generation or propagation select for bottom half of slice. Fixed selection of: * F-LUT output (typically XOR result) * Fixed "1" to always propagate Carry generation or propagation select for top half of slice. Fixed selection of: * G-LUT output (typically XOR result) * Fixed "1" to always propagate Sum generation for bottom half of slice. Inputs from: * F-LUT * CYINIT carry signal from previous stage Result is sent to either the combinatorial or registered output for the top of the slice. XORG Sum generation for top half of slice. Inputs from: * G-LUT * CYMUXF carry signal from previous stage Result is sent to either the combinatorial or registered output for the top of the slice. FAND Multiplier partial product for bottom half of slice. Inputs: * F-LUT F1 input * F-LUT F2 input Result is sent through CY0F to become the carry generate signal into CYMUXF GAND Multiplier partial product for top half of slice. Inputs: * G-LUT G1 input * G-LUT G2 input Result is sent through CY0G to become the carry generate signal into CYMUXG The basic usage of the carry logic is to generate a half-sum in the LUT via an XOR function, which generates or propagates a carry out COUT via the carry mux CYMUXF (or CYMUXG), and then complete the sum with the dedicated XORF (or XORG) gate and the carry input CIN. This structure allows two bits of an arithmetic function in each slice. The CYMUXF (or CYMUXG) can be instantiated using the MUXCY element, and the XORF (or XORG) can be instantiated using the XORCY element.
LUT B MUXCY Sum XORCY CIN
DS312-2_37_021305
CYSELF
CYSELG
XORF
The FAND (or GAND) gate is used for partial product multiplication and can be instantiated using the MULT_AND component. Partial products are generated by two-input AND gates and then added. The carry logic is efficient for the adder, but one of the inputs must be outside the LUT as shown in Figure 20. The FAND (or GAND) gate is used to duplicate one of the partial products, while the LUT generates both partial products and the XOR function, as shown in Figure 21.
LUT Am Bn+1 Am+1 Bn Pm+1 MULT_AND CIN COUT
COUT
A
Figure 20: Using the MUXCY and XORCY in the Carry Logic
DS312-2_39_021305
Figure 21: Using the MULT_AND for Multiplication in Carry Logic
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Functional Description tom portions of the slice are called FFY and FFX, respectively. FFY has a fixed multiplexer on the D input selecting either the combinatorial output Y or the bypass signal BY. FFX selects between the combinatorial output X or the bypass signal BX. The functionality of a slice storage element is identical to that described earlier for the I/O storage elements. All signals have programmable polarity; the default active-High function is described.
The MULT_AND is useful for small multipliers. Larger multipliers can be built using the dedicated 18x18 multiplier blocks (see Dedicated Multipliers).
Storage Elements
The storage element, which is programmable as either a D-type flip-flop or a level-sensitive transparent latch, provides a means for synchronizing data to a clock signal, among other uses. The storage elements in the top and bot-
Table 12: Storage Element Signals
Signal D Description Input. For a flip-flop data on the D input is loaded when R and S (or CLR and PRE) are Low and CE is High during the Low-to-High clock transition. For a latch, Q reflects the D input while the gate (G) input and gate enable (GE) are High and R and S (or CLR and PRE) are Low. The data on the D input during the High-to-Low gate transition is stored in the latch. The data on the Q output of the latch remains unchanged as long as G or GE remains Low. Output. Toggles after the Low-to-High clock transition for a flip-flop and immediately for a latch. Clock for edge-triggered flip-flops. Gate for level-sensitive latches. Clock Enable for flip-flops. Gate Enable for latches. Synchronous Set (Q = High). When the S input is High and R is Low, the flip-flop is set, output High, during the Low-to-High clock (C) transition. A latch output is immediately set, output High. Synchronous Reset (Q = Low); has precedence over Set. Asynchronous Preset (Q = High). When the PRE input is High and CLR is Low, the flip-flop is set, output High, during the Low-to-High clock (C) transition. A latch output is immediately set, output High. Asynchronous Clear (Q = Low); has precedence over Preset to reset Q output Low CLB input for R, S, CLR, or PRE CLB input for opposite of SR. Must be asynchronous or synchronous to match SR.
Q C G CE GE S R PRE CLR SR REV
The control inputs R, S, CE, and C are all shared between the two flip-flops in a slice.
S FDRSE D CE C R
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Table 13: FD Flip-Flop Functionality with Synchronous Reset, Set, and Clock Enable
Inputs R S X 1 0 0 0 CE X X 0 1 1 D X X X 1 0 C X Outputs Q 0 1 No Change 1 0
Q
1 0 0 0 0
Figure 22: FD Flip-Flop Component with Synchronous Reset, Set, and Clock Enable
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Functional Description
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Initialization
The CLB storage elements are initialized at power-up, during configuration, by the global GSR signal, and by the individual SR or REV inputs to the CLB.
Table 14: Slice Storage Element Initialization
Signal SR Description Set/Reset input. Forces the storage element into the state specified by the attribute SRHIGH or SRLOW. SRHIGH forces a logic "1" when SR is asserted. SRLOW forces a logic "0". For each slice, set and reset can be set to be synchronous or asynchronous. Reverse of Set/Reset input. A second input (BY) forces the storage element into the opposite state. The reset condition is predominant over the set condition if both are active. Same synchronous/asynchronous setting as for SR. Global Set/Reset. GSR defaults to active High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN3E element. The initial state after configuration or GSR is defined by a separate INIT0 and INIT1 attribute. By default, setting the SRLOW attribute sets INIT0, and setting the SRHIGH attribute sets INIT1.
ing a 16x1 configuration in one LUT. Multiple SLICEM LUTs can be combined in various ways to store larger amounts of data, including 16x4, 32x2, or 64x1 configurations in one CLB. The fifth and sixth address lines required for the 32-deep and 64-deep configurations, respectively, are implemented using the BX and BY inputs, which connect to the write enable logic for writing and the F5MUX and F6MUX for reading. Writing to distributed RAM is always synchronous to the SLICEM clock (WCLK for distributed RAM) and enabled by the SLICEM SR input which functions as the active-High Write Enable (WE). The read operation is asynchronous, and, therefore, during a write, the output initially reflects the old data at the address being written. The distributed RAM outputs can be captured using the flip-flops within the SLICEM element. The WE write-enable control for the RAM and the CE clock-enable control for the flip-flop are independent, but the WCLK and CLK clock inputs are shared. Because the RAM read operation is asynchronous, the output data always reflects the currently addressed RAM location. A dual-port option combines two LUTs so that memory access is possible from two independent data lines. The same data is written to both 16x1 memories but they have independent read address lines and outputs. The dual-port function is implemented by cascading the G-LUT address lines, which are used for both read and write, to the F-LUT write address lines (WF[4:1] in Figure 12), and by cascading the G-LUT data input D1 through the DIF_MUX in Figure 12 and to the D1 input on the F-LUT. One CLB provides a 16x1 dual-port memory as shown in Figure 23. Any write operation on the D input and any read operation on the SPO output can occur simultaneously with and independently from a read operation on the second read-only port, DPO.
REV
GSR
Distributed RAM
The LUTs in the SLICEM can be programmed as distributed RAM. This type of memory affords moderate amounts of data buffering anywhere along a data path. One SLICEM LUT stores 16 bits (RAM16). The four LUT inputs F[4:1] or G[4:1] become the address lines labeled A[4:1] in the device model and A[3:0] in the design components, provid-
SLICEM
D A[3:0]
16x1 LUT RAM
(Read/ Write)
SPO
WE WCLK
Optional Register
DPRA[3:0]
16x1 LUT RAM
(Read Only)
DPO
Optional Register
DS312-2_41_021305
Figure 23: RAM16X1D Dual-Port Usage
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Table 16: Distributed RAM Signals (Continued)
RAM16X1D WE D WCLK A0 A1 A2 A3 DPRA0 DPRA1 DPRA2 DPRA3 SPO DPO
Signal A0, A1, A2, A3 (A4, A5)
Description The address inputs select the memory cells for read or write. The width of the port determines the required address inputs. The data input provides the new data value to be written into the RAM. The data output O on single-port RAM or the SPO and DPO outputs on dual-port RAM reflects the contents of the memory cells referenced by the address inputs. Following an active write clock edge, the data out (O or SPO) reflects the newly written data.
D O, SPO, and DPO
DS312-2_42_021305
Figure 24: Dual-Port RAM Component Table 15: Dual-Port RAM Function
Inputs WE (mode) 0 (read) 1 (read) 1 (read) 1 (write) 1 (read)
Notes:
1. 2. data_a = word addressed by bits A3-A0. data_d = word addressed by bits DPRA3-DPRA0.
Outputs D X X X D X SPO data_a data_a data_a D data_a DPO data_d data_d data_d data_d data_d
WCLK X 0 1
The INIT attribute can be used to preload the memory with data during FPGA configuration. The default initial contents for RAM is all zeros. If the WE is held Low, the element can be considered a ROM. The ROM function is possible even in the SLICEL. The global write enable signal, GWE, is asserted automatically at the end of device configuration to enable all writable elements. The GWE signal guarantees that the initialized distributed RAM contents are not disturbed during the configuration process. The distributed RAM is useful for smaller amounts of memory. Larger memory requirements can use the dedicated 18Kbit RAM blocks (see Block RAM). For more information on distributed RAM, see XAPP464: "Using Look-Up Tables as Distributed RAM in Spartan-3 FPGAs".
Table 16: Distributed RAM Signals
Signal WCLK Description The clock is used for synchronous writes. The data and the address input pins have setup times referenced to the WCLK pin. Active on the positive edge by default with built-in programmable polarity. The enable pin affects the write functionality of the port. An inactive Write Enable prevents any writing to memory cells. An active Write Enable causes the clock edge to write the data input signal to the memory location pointed to by the address inputs. Active High by default with built-in programmable polarity.
Shift Registers
It is possible to program each SLICEM LUT as a 16-bit shift register (see Figure 25). Used in this way, each LUT can delay serial data anywhere from 1 to 16 clock cycles without using any of the dedicated flip-flops. The resulting programmable delays can be used to balance the timing of data pipelines. The SLICEM LUTs cascade from the G-LUT to the F-LUT through the DIFMUX (see Figure 12). SHIFTIN and SHIFTOUT lines cascade a SLICEM to the SLICEM below to form larger shift registers. The four SLICEM LUTs of a single CLB can be combined to produce delays up to 64 clock cycles. It is also possible to combine shift registers across more than one CLB.
WE
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Functional Description
I
R
SHIFTIN
SRLC16 D CE CLK A0 A1 A2 A3
SRLC16E Q Q15
SHIFT-REG A[3:0] 4 A[3:0] D MC15 D WS DI (BY) WSG CE (SR) CLK WE CK (optional) DI Q Output Registered Output
DS312-2_43_021305
Figure 26: SRL16 Shift Register Component with Cascade and Clock Enable
The functionality of the shift register is shown in Table 17. The SRL16 shifts on the rising edge of the clock input when the Clock Enable control is High. This shift register cannot be initialized either during configuration or during operation except by shifting data into it. The clock enable and clock inputs are shared between the two LUTs in a SLICEM. The clock enable input is automatically kept active if unused.
SHIFTOUT or YB
X465_03_040203
Figure 25: Logic Cell SRL16 Structure
Each shift register provides a shift output MC15 for the last bit in each LUT, in addition to providing addressable access to any bit in the shift register through the normal D output. The address inputs A[3:0] are the same as the distributed RAM address lines, which come from the LUT inputs F[4:1] or G[4:1]. At the end of the shift register, the CLB flip-flop can be used to provide one more shift delay for the addressable bit. The shift register element is known as the SRL16 (Shift Register LUT 16-bit), with a `C' added to signify a cascade ability (Q15 output) and `E' to indicate a Clock Enable. See Figure 26 for an example of the SRLC16E component.
Table 17: SRL16 Shift Register Function
Inputs Am Am Am
Notes:
1. m = 0, 1, 2, 3.
Outputs D X D Q Q[Am] Q[Am-1] Q15 Q[15] Q[15]
CLK X
CE 0 1
For more information on the SRL16, refer to XAPP465: "Using Look-Up Tables as Shift Registers (SRL16) in Spartan-3 FPGAs".
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Functional Description block RAM's shared connectivity with the multipliers are located in XAPP463.
Block RAM
Spartan-3E devices incorporate 4 to 36 dedicated block RAMs, which are organized as dual-port configurable 18 Kbit blocks. Functionally, the block RAM is identical to the Spartan-3 architecture block RAM. Block RAM synchronously stores large amounts of data while distributed RAM, previously described, is better suited for buffering small amounts of data anywhere along signal paths. This section describes basic block RAM functions. For detailed implementation information, refer to XAPP463: "Using Block RAM in Spartan-3 Series FPGAs". Each block RAM is configurable by setting the content's initial values, default signal value of the output registers, port aspect ratios, and write modes. Block RAM can be used in single-port or dual-port modes.
The Internal Structure of the Block RAM
The block RAM has a dual port structure. The two identical data ports called A and B permit independent access to the common block RAM, which has a maximum capacity of 18,432 bits, or 16,384 bits with no parity bits (see parity bits description in Table 19). Each port has its own dedicated set of data, control, and clock lines for synchronous read and write operations. There are four basic data paths, as shown in Figure 27: 1. Write to and read from Port A 2. Write to and read from Port B 3. Data transfer from Port A to Port B 4. Data transfer from Port B to Port A
Arrangement of RAM Blocks on Die
The block RAMs are located together with the multipliers on the die in one or two columns depending on the size of the device. The XC3S100E has one column of block RAM. The Spartan-3E devices ranging from the XC3S250E to XC3S1600E have two columns of block RAM. Table 18 shows the number of RAM blocks, the data storage capacity, and the number of columns for each device. Row(s) of CLBs are located above and below each block RAM column.
Write 4 Read
Read 3 Write
Spartan-3E Dual-Port Block RAM
Write 1 Read
Port B
Port A
Write 2 Read
DS312-2_01_020705
Table 18: Number of RAM Blocks by Device
Total Number of RAM Blocks 4 12 20 28 36 Total Addressable Locations (bits) 73,728 221,184 368,640 516,096 663,552 Number of Columns 1 2 2 2 2
Figure 27: Block RAM Data Paths
Device XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E
Number of Ports
A choice among primitives determines whether the block RAM functions as dual- or single-port memory. A name of the form RAMB16_S[wA]_S[wB] calls out the dual-port primitive, where the integers wA and wB specify the total data path width at ports A and B, respectively. Thus, a RAMB16_S9_S18 is a dual-port RAM with a 9-bit Port A and an 18-bit Port B. A name of the form RAMB16_S[w] identifies the single-port primitive, where the integer w specifies the total data path width of the lone port A. A RAMB16_S18 is a single-port RAM with an 18-bit port.
Immediately adjacent to each block RAM is an embedded 18x18 hardware multiplier. The upper 16 bits of the block RAM's Port A Data input bus are shared with the upper 16 bits of the A multiplicand input bus of the multiplier. Similarly, the upper 16 bits of Port B's data input bus are shared with the B multiplicand input bus of the multiplier. Details on the
Port Aspect Ratios
Each port of the block RAM can be configured independently to select a number of different possible widths for the data input (DI) and data output (DO) signals as shown in Table 19.
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Functional Description
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Table 19: Port Aspect Ratios
Total Data Path Width (w bits) 1 2 4 9 18 36
Notes:
1. 2. 3. 4. The width of the total data path (w) is the sum of the DI/DO bus width (w-p) and any parity bits (p). The width selection made for the DI/DO bus determines the number of address lines (r) according to the relationship expressed as: r = 14 - [log(w-p)/log(2)]. The number of address lines delimits the total number (n) of addressable locations or depth according to the following equation: n = 2r. The product of w and n yields the total block RAM capacity.
DI/DO Data Bus Width (w-p bits)1 1 2 4 8 16 32
DIP/DOP Parity Bus Width (p bits) 0 0 0 1 2 4
ADDR Bus Width (r bits)2 14 13 12 11 10 9
DI/DO [w-p-1:0] [0:0] [1:0] [3:0] [7:0] [15:0] [31:0]
DIP/DOP [p-1:0] [0:0] [1:0] [3:0]
ADDR [r-1:0] [13:0] [12:0] [11:0] [10:0] [9:0] [8:0]
No. of Addressable Locations (n)3 16,384 8,192 4,096 2,048 1,024 512
Block RAM Capacity (w*n bits)4 16,384 16,384 16,384 18,432 18,432 18,432
If the data bus width of Port A differs from that of Port B, the block RAM automatically performs a bus-matching function as described in Figure 28. When data is written to a port with a narrow bus and then read from a port with a wide bus, the latter port effectively combines "narrow" words to form "wide" words. Similarly, when data is written into a port with a wide bus and then read from a port with a narrow bus, the latter port divides "wide" words to form "narrow" words. Par-
ity bits are not available if the data port width is configured as x4, x2, or x1. For example, if a x36 data word (32 data, 4 parity) is addressed as two x18 halfwords (16 data, 2 parity), the parity bits associated with each data byte are mapped within the block RAM to the appropriate parity bits. The same effect happens when the x36 data word is mapped as four x9 words.
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Parity
35 34 33 32 31 24 23
Data
16 15 87 0
Address
512x36
P3 P2 P1 P0
Byte 3
Byte 2
17 16 15
Byte 1
87
Byte 0
0
0
1Kx18
Pa r (16 ity O pti Kb 2K bits its da onal pa ta, r ity )
P3 P2 P1 P0
Byte 3 Byte 1
8 7
Byte 2 Byte 0
0
1 0
P3
Byte 3 Byte 2 Byte 1 Byte 0
3210
2Kx9
P2 P1 P0
3 2 1 0
7 6 53 4 B y te 3210
7 6
4Kx4
7 6 50 4 yt e 3B2 1 0
10
1 0
7 5 3 1
6 4 2 0
F E D C
No Parity (16Kbits data)
8Kx2
7 5 3 1 6 4 2 0
0
Byte 3 Byte 0
3 2 1 0
7 6 5 4
1F 1E 1D 1C
16Kx1
3 2 1 0
Byte 3
3 2 1 0
DS312-2_02_020705
Figure 28: Data Organization and Bus-matching Operation with Different Port Widths on Port A and Port B
Block RAM Port Signal Definitions
Representations of the dual-port primitive RAMB16_S[wA]_S[wB] and the single-port primitive RAMB16_S[w] with their associated signals are shown in Figure 29a and Figure 29b, respectively. These signals are
defined in Table 20. The control signals (WE, EN, CLK, and SSR) on the block RAM are active High. However, optional inverters on the control signals change the polarity of the active edge to active Low.
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Byte 0
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Functional Description
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WEA ENA SSRA CLKA ADDRA[rA-1:0] DIA[wA-pA-1:0] DIPA[pA-1:0]
RAMB16_wA_wB
DOPA[pA-1:0] DOA[wA-pA-1:0]
WEB ENB SSRB CLKB ADDRB[rB-1:0] DIB[wB-pB-1:0] DIPB[pB-1:0]
DOPB[pB-1:0] DOB[wB-pB-1:0]
WE EN SSR CLK ADDR[r-1:0] DI[w-p-1:0] DIP[p-1:0]
RAMB16_Sw
DOP[p-1:0] DO[w-p-1:0]
(a) Dual-Port
Notes:
1. 2. 3. 4.
(b) Single-Port
DS312-2_03_021305
wA and wB are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively. pA and pB are integers that indicate the number of data path lines serving as parity bits. rA and rB are integers representing the address bus width at ports A and B, respectively. The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
Figure 29: Block RAM Primitives
Table 20: Block RAM Port Signals
Signal Description Address Bus Port A Signal Name ADDRA Port B Signal Name ADDRB
Direction Input
Function The Address Bus selects a memory location for read or write operations. The width (w) of the port's associated data path determines the number of available address lines (r), as per Table 18. Data at the DI input bus is written to the RAM location specified by the address input bus (ADDR) during the active edge of the CLK input, when the clock enable (EN) and write enable (WE) inputs are active. It is possible to configure a port's DI input bus width (w-p) based on Table 18. This selection applies to both the DI and DO paths of a given port.
Data Input Bus
DIA
DIB
Input
Parity Data Input(s)
DIPA
DIPB
Input
Parity inputs represent additional bits included in the data input path. Although referred to herein as "parity" bits, the parity inputs and outputs have no special functionality for generating or checking parity and can be used as additional data bits. The number of parity bits `p' included in the DI (same as for the DO bus) depends on a port's total data path width (w). See Table 18.
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Table 20: Block RAM Port Signals (Continued)
Signal Description Data Output Bus Port A Signal Name DOA Port B Signal Name DOB
Direction Output
Function Data is written to the DO output bus from the RAM location specified by the address input bus, ADDR. See the DI signal description for DO port width configurations. Basic data access occurs on the active edge of the CLK when WE is inactive and EN is active. The DO outputs mirror the data stored in the address ADDR memory location. Data access with WE active if the WRITE_MODE attribute is set to the value: WRITE_FIRST, which accesses data after the write takes place. READ_FIRST accesses data before the write occurs. A third attribute, NO_CHANGE, latches the DO outputs upon the assertion of WE. See Block RAM Data Operations for details on the WRITE_MODE attribute.
Parity Data Output(s)
DOPA
DOPB
Output
Parity outputs represent additional bits included in the data input path. The number of parity bits `p' included in the DI bus (same as for the DO bus) depends on a port's total data path width (w). See the DIP signal description for configuration details. When asserted together with EN, this input enables the writing of data to the RAM. When WE is inactive with EN asserted, read operations are still possible. In this case, a latch passes data from the addressed memory location to the DO outputs. When asserted, this input enables the CLK signal to perform read and write operations to the block RAM. When inactive, the block RAM does not perform any read or write operations. When asserted, this pin forces the DO output latch to the value of the SRVAL attribute. It is synchronized to the CLK signal. This input accepts the clock signal to which read and write operations are synchronized. All associated port inputs are required to meet setup times with respect to the clock signal's active edge. The data output bus responds after a clock-to-out delay referenced to the clock signal's active edge.
Write Enable
WEA
WEB
Input
Clock Enable
ENA
ENB
Input
Set/Reset Clock
SSRA CLKA
SSRB CLKB
Input Input
Block RAM Attribute Definitions
A block RAM has a number of attributes that control its behavior as shown in Table 21.
Table 21: Block RAM Attributes
Function Initial Content for Data Memory, Loaded during Configuration Initial Content for Parity Memory, Loaded during Configuration Data Output Latch Initialization Attribute INITxx (INIT_00 through INIT3F) INITPxx (INITP_00 through INITP0F) INIT (single-port) INITA, INITB (dual-port) Possible Values Each initialization string defines 32 hex values of the 16384-bit data memory of the block RAM. Each initialization string defines 32 hex values of the 2048-bit parity data memory of the block RAM. Hex value the width of the chosen port.
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Functional Description
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Table 21: Block RAM Attributes (Continued)
Function Data Output Latch Synchronous Set/Reset Value Data Output Latch Behavior during Write (see Block RAM Data Operations) Attribute SRVAL (single-port) SRVAL_A, SRVAL_B (dual-port) WRITE_MODE Possible Values Hex value the width of the chosen port.
WRITE_FIRST, READ_FIRST, NO_CHANGE
Block RAM Data Operations
Writing data to and accessing data from the block RAM are synchronous operations that take place independently on each of the two ports. Table 22 describes the data operations of each port as a result of the block RAM control signals in their default active-High edges.
The waveforms for the write operation are shown in the top half of Figure 30, Figure 31, and Figure 32. When the WE and EN signals enable the active edge of CLK, data at the DI input bus is written to the block RAM location addressed by the ADDR lines.
Table 22: Block RAM Function Table
Input Signals GSR EN SSR WE CLK ADDR DIP DI Output Signals DOP DO RAM Data Parity Data
Immediately After Configuration Loaded During Configuration X X INITP_xx INIT_xx
Global Set/Reset Immediately After Configuration 1 X X X X X X X INIT INIT No Chg No Chg
RAM Disabled 0 0 X X X X X X No Chg No Chg No Chg No Chg
Synchronous Set/Reset 0 1 1 0 X X X SRVAL SRVAL No Chg No Chg
Synchronous Set/Reset During Write RAM 0 1 1 1 addr pdata Data SRVAL SRVAL RAM(addr) pdata RAM(addr) data
Read RAM, no Write Operation 0 1 0 0 addr X X RAM(pdata) RAM(data) No Chg No Chg
Write RAM, Simultaneous Read Operation 0 1 0 1 addr pdata Data pdata WRITE_MODE = WRITE_FIRST data RAM(addr) pdata RAM(addr) data
WRITE_MODE = READ_FIRST RAM(data) RAM(data) RAM(addr) pdata RAM(addr) pdata
WRITE_MODE = NO_CHANGE No Chg No Chg RAM(addr) pdata RAM(addr) pdata
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Functional Description portions of Figure 30, Figure 31, and Figure 32 during which WE is Low. Data also can be accessed on the DO outputs when asserting the WE input based on the value of the WRITE_MODE attribute as described in Table 23.
There are a number of different conditions under which data can be accessed at the DO outputs. Basic data access always occurs when the WE input is inactive. Under this condition, data stored in the memory location addressed by the ADDR lines passes through a output latch to the DO outputs. The timing for basic data access is shown in the
Table 23: WRITE_MODE Effect on Data Output Latches During Write Operations
Write Mode WRITE_FIRST Read After Write READ_FIRST Read Before Write Effect on Same Port Data on DI and DIP inputs is written into specified RAM location and simultaneously appears on DO and DOP outputs. Data from specified RAM location appears on DO and DOP outputs. Data on DI and DIP inputs is written into specified location. NO_CHANGE No Read on Write Data on DO and DOP outputs remains unchanged. Data on DI and DIP inputs is written into specified location. Invalidates data on DO and DOP outputs. Effect on Opposite Port (dual-port only with same address) Invalidates data on DO and DOP outputs.
Data from specified RAM location appears on DO and DOP outputs.
Data_in
DI
Internal Memory
DO
Data_out = Data_in
CLK
WE DI ADDR DO
XXXX 1111 2222 XXXX
aa
bb
cc
dd
0000
MEM(aa)
1111
2222
MEM(dd)
EN
DISABLED READ WRITE MEM(bb)=1111 WRITE MEM(cc)=2222 READ
DS312-2_05_020905
Figure 30: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
Setting the WRITE_MODE attribute to a value of WRITE_FIRST, data is written to the addressed memory location on an enabled active CLK edge and is also passed to the DO outputs. WRITE_FIRST timing is shown in the portion of Figure 30 during which WE is High. Setting the WRITE_MODE attribute to a value of READ_FIRST, data already stored in the addressed location passes to the DO outputs before that location is overwritten with new data from the DI inputs on an enabled active CLK edge. READ_FIRST timing is shown in the portion of Figure 31 during which WE is High.
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Functional Description
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Data_in
DI
Internal Memory
DO
Prior stored data
CLK
WE DI ADDR DO EN
DISABLED READ WRITE MEM(bb)=1111 WRITE MEM(cc)=2222 READ
DS312-2_06_020905
XXXX
1111
2222
XXXX
aa
bb
cc
dd
0000
MEM(aa)
old MEM(bb)
old MEM(cc)
MEM(dd)
Figure 31: Waveforms of Block RAM Data Operations with READ_FIRST Selected
Data_in
DI
Internal Memory
DO
No change during write
CLK WE DI ADDR DO
XXXX 1111 2222 XXXX
aa
bb
cc
dd
0000
MEM(aa)
MEM(dd)
EN
DISABLED READ WRITE MEM(bb)=1111 WRITE MEM(cc)=2222 READ
DS312-2_07_020905
Figure 32: Waveforms of Block RAM Data Operations with NO_CHANGE Selected
Setting the WRITE_MODE attribute to a value of NO_CHANGE, puts the DO outputs in a latched state when asserting WE. Under this condition, the DO outputs retain the data driven just before WE is asserted. NO_CHANGE timing is shown in the portion of Figure 32 during which WE is High.
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Functional Description Implement multipliers with inputs less than 18 bits by sign-extending the inputs (i.e., replicating the most-significant bit). Wider multiplication operations are performed by combining the dedicated multipliers and slice-based logic in any viable combination or by time-sharing a single multiplier. Perform unsigned multiplication by restricting the inputs to the positive range. Tie the most-significant bit Low and represent the unsigned value in the remaining 17 lesser-significant bits. As shown in Figure 33, each multiplier block has optional registers on each of the multiplier inputs and the output. The registers are named AREG, BREG, and PREG and can be used in any combination. The clock input is common to all the registers within a block, but each register has an independent clock enable and synchronous reset controls making them ideal for storing data samples and coefficients. When used for pipelining, the registers boost the multiplier clock rate, beneficial for higher performance applications. Figure 33 illustrates the principle features of the multiplier block.
Dedicated Multipliers
The Spartan-3E devices provide 4 to 36 dedicated multiplier blocks per device. The multipliers are located together with the block RAM in one or two columns depending on device density. See Arrangement of RAM Blocks on Die for details on the location of these blocks and their connectivity. The multiplier blocks primarily perform two's complement numerical multiplication but can also perform some less obvious applications such as simple data storage and barrel shifting. Logic slices also implement efficient small multipliers and thereby supplement the dedicated multipliers. The Spartan-3E dedicated multiplier blocks have additional features beyond those provided in Spartan-3 FPGAs. Each multiplier performs the principle operation P = A x B, where `A' and `B' are 18-bit words in two's complement form, and `P' is the full-precision 36-bit product, also in two's complement form. The 18-bit inputs represent values ranging from -131,07210 to +131,07110 with a resulting product ranging from -17,179,738,11210 to +17,179,869,18410.
AREG (Optional) CEA A[17:0] CE D Q
RST CEP RSTA BREG (Optional) CEB B[17:0] CE D Q RSTP
PREG (Optional) CE D Q P[35:0]
X
RST
RST RSTB CLK
DS312-2_27_021205
Figure 33: Principle Ports and Functions of Dedicated Multiplier Blocks
Use the MULT18X18SIO primitive shown in Figure 34 to instantiate a multiplier within a design. Although high-level logic synthesis software usually automatically infers a multiplier, adding the pipeline registers usually requires the MULT18X18SIO primitive. Connect the appropriate signals to the MULT18X18SIO multiplier ports and set the individual AREG, BREG, and PREG attributes to `1' to insert the associated register, or to 0 to remove it and make the signal path combinatorial.
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Functional Description
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MULT18X18SIO A[17:0] B[17:0] CEA CEB CEP CLK RSTA RSTB RSTP BCIN[17:0] BCOUT[17:0]
DS312-2_28_021205
P[35:0]
The MULT18X18SIO primitive has two additional ports called BCIN and BCOUT to cascade or share the multiplier's `B' input among several multiplier bocks. The 18-bit BCIN "cascade" input port offers an alternate input source from the more typical `B' input. The B_INPUT attribute specifies whether the specific implementation uses the BCIN or `B' input path. Setting B_INPUT to DIRECT chooses the `B' input. Setting B_INPUT to CASCADE selects the alternate BCIN input. The BREG register then optionally holds the selected input value, if required. BCOUT is an 18-bit output port that always reflects the value that is applied to the multiplier's second input, which is either the `B' input, the cascaded value from the BCIN input, or the output of the BREG if it is inserted. Figure 35 illustrates the four possible configurations using different settings for the B_INPUT attribute and the BREG attribute.
Figure 34: MULT18X18SIO Primitive
BCOUT[17:0] BREG CEB CE D CLK RST RSTB BCIN[17:0] BREG = 1 B_INPUT = CASCADE Q
BCOUT[17:0]
X
X
BREG = 0 B_INPUT = CASCADE
BCIN[17:0] BCOUT[17:0]
BCOUT[17:0] BREG CEB B[17:0] CLK RST RSTB BREG = 1 B_INPUT = DIRECT CE D Q
X
B[17:0]
X
BREG = 0 B_INPUT = DIRECT
DS312-2_29_021505
Figure 35: Four Configurations of the B Input
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Functional Description
The BCIN and BCOUT ports have associated dedicated routing that connects adjacent multipliers within the same column. Via the cascade connection, the BCOUT port of one multiplier block drives the BCIN port of the multiplier block directly above it. There is no connection to the BCIN port of the bottom-most multiplier block in a column or a connection from the BCOUT port of the top-most block in a column. As an example, Figure 36 shows the multiplier cascade capability within the XC3S100E FPGA, which has a single column of multiplier, four blocks tall. For clarity, the figure omits the register control inputs.
BCOUT A P B B_INPUT = CASCADE BCIN
BCOUT A P B B_INPUT = CASCADE BCIN
BCOUT A P B B_INPUT = CASCADE BCIN
BCOUT A P B B_INPUT = DIRECT BCIN
DS312-2_30_021505
Figure 36: Multiplier Cascade Connection
When using the BREG register, the cascade connection forms a shift register structure typically used in DSP algorithms such as direct-form FIR filters. When the BREG register is omitted, the cascade structure essentially feeds the same input value to more than one multiplier. This parallel connection serves to create wide-input multipliers, implement transpose FIR filters, and is used in any application that requires that several multipliers have the same input value.
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Functional Description Table 24 defines each port of the MULT18X18SIO primitive.
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Table 24: MULT18X18SIO Embedded Multiplier Primitives Description
Signal Name A[17:0] Direction Input Function The primary 18-bit two's complement value for multiplication. The block multiplies by this value asynchronously if the optional AREG and PREG registers are omitted. When AREG and/or PREG are used, the value provided on this port is qualified by the rising edge of CLK, subject to the appropriate register controls. The second 18-bit two's complement value for multiplication if the B_INPUT attribute is set to DIRECT. The block multiplies by this value asynchronously if the optional BREG and PREG registers are omitted. When BREG and/or PREG are used, the value provided on this port is qualified by the rising edge of CLK, subject to the appropriate register controls. The second 18-bit two's complement value for multiplication if the B_INPUT attribute is set to CASCADE. The block multiplies by this value asynchronously if the optional BREG and PREG registers are omitted. When BREG and/or PREG are used, the value provided on this port is qualified by the rising edge of CLK, subject to the appropriate register controls. The 36-bit two's complement product resulting from the multiplication of the two input values applied to the multiplier. If the optional AREG, BREG and PREG registers are omitted, the output operates asynchronously. Use of PREG causes this output to respond to the rising edge of CLK with the value qualified by CEP and RSTP. If PREG is omitted, but AREG and BREG are used, this output responds to the rising edge of CLK with the value qualified by CEA, RSTA, CEB, and RSTB. If PREG is omitted and only one of AREG or BREG is used, this output responds to both asynchronous and synchronous events. The value being applied to the second input of the multiplier. When the optional BREG register is omitted, this output responds asynchronously in response to changes at the B[17:0] or BCIN[17:0] ports according to the setting of the B_INPUT attribute. If BREG is used, this output responds to the rising edge of CLK with the value qualified by CEB and RSTB. Clock enable qualifier for the optional AREG register. The value provided on the A[17:0] port is captured by AREG in response to a rising edge of CLK when this signal is High, provided that RSTA is Low. Synchronous reset for the optional AREG register. AREG content is forced to the value zero in response to a rising edge of CLK when this signal is High. Clock enable qualifier for the optional BREG register. The value provided on the B[17:0] or BCIN[17:0] port is captured by BREG in response to a rising edge of CLK when this signal is High, provided that RSTB is Low. Synchronous reset for the optional BREG register. BREG content is forced to the value zero in response to a rising edge of CLK when this signal is High. Clock enable qualifier for the optional PREG register. The value provided on the output of the multiplier port is captured by PREG in response to a rising edge of CLK when this signal is High, provided that RSTP is Low. Synchronous reset for the optional PREG register. PREG content is forced to the value zero in response to a rising edge of CLK when this signal is High.
B[17:0]
Input
BCIN[17:0]
Input
P[35:0]
Output
BCOUT[17:0]
Output
CEA
Input
RSTA CEB
Input Input
RSTB CEP
Input Input
RSTP
Notes:
1.
Input
The control signals CLK, CEA, RSTA, CEB, RSTB, CEP, and RSTP have the option of inverted polarity.
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Functional Description The DCM supports three major functions: * Clock-skew Elimination: Clock skew describes the extent to which clock signals may, under normal circumstances, deviate from zero-phase alignment. It occurs when slight differences in path delays cause the clock signal to arrive at different points on the die at different times. This clock skew can increase set-up and hold time requirements as well as clock-to-out time, which may be undesirable in applications operating at a high frequency, when timing is critical. The DCM eliminates clock skew by aligning the output clock signal it generates with another version of the clock signal that is fed back. As a result, the two clock signals establish a zero-phase relationship. This effectively cancels out clock distribution delays that might lie in the signal path leading from the clock output of the DCM to its feedback input. Frequency Synthesis: Provided with an input signal, the DCM can generate a wide range of different output clock frequencies. This is accomplished by either multiplying and/or dividing the frequency of the input clock signal by any of several different factors. Phase Shifting: The DCM provides the ability to shift the phase of all its output clock signals with respect to its input clock signal.
Digital Clock Managers (DCMs)
Differences from the Spartan-3 Architecture
* * * Spartan-3E FPGAs have two, four, or eight DCMs, depending on device size. The Spartan-3E DCM has a maximum phase shift range of 180. The Spartan-3 DCM range is 360. The Spartan-3E DLL supports lower input frequencies, down to 5 MHz. Spartan-3 DLLs supports down to 24 MHz.
Overview
Spartan-3E Digital Clock Managers (DCMs) provide flexible, complete control over clock frequency, phase shift and skew. To accomplish this, the DCM employs a Delay-Locked Loop (DLL), a fully digital control system that uses feedback to maintain clock signal characteristics with a high degree of precision despite normal variations in operating temperature and voltage. This section provides a fundamental description of the DCM. See XAPP462: "Using Digital Clock Managers (DCMs) in Spartan-3 Series FPGAs" for further information. The XC3S100E FPGA has two DCMs, one at the top and one at the bottom of the device. The XC3S250E and XC3S500E FPGAs each include four DCMs, two at the top and two at the bottom. The XC3S1200E and XC3S1600E FPGAs contain eight DCMs with two on each edge (see also Figure 42). The DCM in Spartan-3E FPGAs is surrounded by CLBs within the logic array and is no longer located at the top and bottom of a column of block RAM as in the Spartan-3 architecture,. The Digital Clock Manager is instantiated into a design as the "DCM" primitive.
*
*
The DCM has four functional components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), the Phase Shifter (PS), and the Status Logic. Each component has its associated signals, as shown in Figure 37.
DCM
PSINCDEC PSEN PSCLK Phase Shifter PSDONE
Output Stage
CLKIN Input Stage Delay Taps
CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180
8
Clock Distribution Delay
CLKFB
DFS DLL RST Status Logic
LOCKED STATUS [7:0]
DS099-2_07_040103
Figure 37: DCM Functional Blocks and Associated Signals
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Functional Description
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CLK0 Output Section CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV
CLKIN
Delay 1
Delay 2
Delay n-1
Delay n
Control
LOCKED
CLKFB RST
Phase Detection
DS099-2_08_041103
Figure 38: Simplified Functional Diagram of DLL
Table 25: DLL Signals
Signal CLKIN CLKFB CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV Direction Input Input Output Output Output Output Output Output Output Accepts original clock signal. Accepts either CLK0 or CLK2X as the feedback signal. (Set CLK_FEEDBACK attribute accordingly). Generates a clock signal with same frequency and phase as CLKIN. Generates a clock signal with same frequency as CLKIN, only phase-shifted 90. Generates a clock signal with same frequency as CLKIN, only phase-shifted 180. Generates a clock signal with same frequency as CLKIN, only phase-shifted 270. Generates a clock signal with same phase as CLKIN, only twice the frequency. Generates a clock signal with twice the frequency of CLKIN, phase-shifted 180 with respect to CLKIN. Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower frequency clock signal that is phase-aligned to CLKIN. neously. Signals that initialize and report the state of the DLL are discussed in the Status Logic Component section. The clock signal supplied to the CLKIN input serves as a reference waveform. The DLL seeks to align the rising-edge of feedback signal at the CLKFB input with the rising-edge of CLKIN input. When eliminating clock skew, the common approach to using the DLL is as follows: The CLK0 signal is passed through the clock distribution network to all the registers it synchronizes. These registers are either internal or external to the FPGA. After passing through the clock distribution network, the clock signal returns to the DLL via a feedback line called CLKFB. The control block inside the DLL measures the phase error between CLKFB and CLKIN. Description
Delay-Locked Loop (DLL)
The most basic function of the DLL component is to eliminate clock skew. The main signal path of the DLL consists of an input stage, followed by a series of discrete delay elements or taps, which in turn leads to an output stage. This path together with logic for phase detection and control forms a system complete with feedback as shown in Figure 38. In Spartan-3E FPGAs, the DLL is implemented using a counter-based delay line. The DLL component has two clock inputs, CLKIN and CLKFB, as well as seven clock outputs, CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as described in Table 25. The clock outputs drive simulta40
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Functional Description
This phase error is a measure of the clock skew that the clock distribution network introduces. The control block activates the appropriate number of delay elements to cancel out the clock skew. Once the DLL has brought the CLK0 signal in phase with the CLKIN signal, it asserts the LOCKED output, indicating a lock on to the CLKIN signal.
DLL Attributes and Related Functions
A number of different functional options can be set for the DLL component through the use of the attributes described in Table 26. Each attribute is described in detail in the sections that follow:
Table 26: DLL Attributes
Attribute CLK_FEEDBACK CLKIN_DIVIDE_BY_2 CLKDV_DIVIDE Description Chooses either the CLK0 or CLK2X output to drive the CLKFB input Halves the frequency of the CLKIN signal just as it enters the DCM Selects the constant used to divide the CLKIN input frequency to generate the CLKDV output frequency Enables 50% duty cycle correction for the CLK0, CLK90, CLK180, and CLK270 outputs NONE, 1X, 2X TRUE, FALSE 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0, 6.5, 7.0, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16 TRUE, FALSE Values
DUTY_CYCLE_CORRECTION
DLL Clock Input Connections
An external clock source enters the FPGA using a Global Clock Input Buffer (IBUFG), which directly accesses the global clock network or via an Input Buffer (IBUF). Clock signals within the FPGA drive a global clock net using a Global Clock Multiplexer Buffer (BUFGMUX). The global clock net connects directly to the CLKIN input. The internal and external connections are shown in Figure 39a and Figure 39c, respectively. A differential clock (e.g., LVDS) can serve as an input to CLKIN.
DLL Clock Output and Feedback Connections
As many as four of the nine DCM clock outputs can simultaneously drive four of the BUFGMUX buffers on the same die edge. All DCM clock outputs can simultaneously drive general routing resources, including interconnect leading to OBUF buffers.
The feedback loop is essential for DLL operation and is established by driving the CLKFB input with either the CLK0 or the CLK2X signal so that any undesirable clock distribution delay is included in the loop. It is possible to use either of these two signals for synchronizing any of the seven DLL outputs: CLK0, CLK90, CLK180, CLK270, CLKDV, CLK2X, or CLK2X180. The value assigned to the CLK_FEEDBACK attribute must agree with the physical feedback connection: a value of 1X for the CLK0 case, 2X for the CLK2X case. If the DCM is used in an application that does not require the DLL -- that is, only the DFS is used -- then there is no required feedback loop so CLK_FEEDBACK is set to NONE. There are two basic cases that determine how to connect the DLL clock outputs and feedback connections: on-chip synchronization and off-chip synchronization, which are illustrated in Figure 39a through Figure 39d.
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Functional Description
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FPGA
BUFGMUX BUFG CLKIN CLK90 CLK180 CLK270 CLKDV CLK2X CLK2X180 CLK0 BUFGMUX CLK0 BUFG CLKIN
Clock Net Delay
FPGA
BUFGMUX CLK0 CLK90 CLK180 CLK270 CLKDV CLK2X180 CLK2X BUFGMUX CLK2X
DCM
CLKFB
DCM
CLKFB
Clock Net Delay
(a) On-Chip with CLK0 Feedback FPGA
IBUFG CLKIN CLK90 CLK180 CLK270 CLKDV CLK2X CLK2X180 CLK0 OBUF OBUF
(b) On-Chip with CLK2X Feedback FPGA
IBUFG CLKIN CLK0 CLK90 CLK180 CLK270 CLKDV CLK2X180 CLK2X OBUF OBUF
DCM
CLKFB IBUFG
Clock Net Delay
DCM
CLKFB IBUFG
Clock Net Delay
CLK0
CLK2X
(c) Off-Chip with CLK0 Feedback
(d) Off-Chip with CLK2X Feedback
DS099-2_09_082104
Figure 39: Input Clock, Output Clock, and Feedback Connections for the DLL
In the on-chip synchronization case in Figure 39a and Figure 39b, it is possible to connect any of the DLL's seven output clock signals through general routing resources to the FPGA's internal registers. Either a Global Clock Buffer (BUFG) or a BUFGMUX affords access to the global clock network. As shown in Figure 39a, the feedback loop is created by routing CLK0 (or CLK2X, in Figure 39b to a global clock net, which in turn drives the CLKFB input. In the off-chip synchronization case in Figure 39c and Figure 39d, CLK0 (or CLK2X) plus any of the DLL's other output clock signals exit the FPGA using output buffers (OBUF) to drive an external clock network plus registers on the board. As shown in Figure 39c, the feedback loop is formed by feeding CLK0 (or CLK2X, in Figure 39d) back into the FPGA using an IBUFG, which directly accesses the global clock network, or an IBUF. Then, the global clock net is connected directly to the CLKFB input.
Coarse Phase Shift Outputs of the DLL Component
In addition to CLK0 for zero-phase alignment to the CLKIN signal, the DLL also provides the CLK90, CLK180, and CLK270 outputs for 90, 180, and 270 phase-shifted signals, respectively. These signals are described in Table 25. Their relative timing is shown in Figure 40. For control in finer increments than 90, see Phase Shifter (PS).
Basic Frequency Synthesis Outputs of the DLL Component
The DLL component provides basic options for frequency multiplication and division in addition to the more flexible synthesis capability of the DFS component, described in a later section. These operations result in output clock signals with frequencies that are either a fraction (for division) or a multiple (for multiplication) of the incoming clock frequency. The CLK2X output produces an in-phase signal that is twice the frequency of CLKIN. The CLK2X180 output also doubles the frequency, but is 180 out-of-phase with respect to CLKIN. The CLKDIV output generates a clock frequency that is a predetermined fraction of the CLKIN frequency. The CLKDV_DIVIDE attribute determines the factor used to divide the CLKIN frequency. The attribute can be set to var-
Accommodating High Input Frequencies
If the frequency of the CLKIN signal is high such that it exceeds the maximum permitted, divide it down to an acceptable value using the CLKIN_DIVIDE_BY_2 attribute. When this attribute is set to TRUE, the CLKIN frequency is divided by a factor of two just as it enters the DCM.
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Functional Description 2. The fCLKFX frequency calculated from the above expression accords with the DCM's operating frequency specifications. For example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, then the frequency of the output clock signal is 5/3 that of the input clock signal.
o o o o o o o o o
ious values as described in Table 26. The basic frequency synthesis outputs are described in Table 25.
Duty Cycle Correction of DLL Clock Outputs
The CLK2X(1), CLK2X180, and CLKDV(2) output signals ordinarily exhibit a 50% duty cycle - even if the incoming CLKIN signal has a different duty cycle. Fifty-percent duty cycle means that the High and Low times of each clock cycle are equal. The DUTY_CYCLE_CORRECTION attribute determines whether or not duty cycle correction is applied to the CLK0, CLK90, CLK180, and CLK270 outputs. If DUTY_CYCLE_CORRECTION is set to TRUE, then the duty cycle of these four outputs is corrected to 50%. If DUTY_CYCLE_CORRECTION is set to FALSE, then these outputs exhibit the same duty cycle as the CLKIN signal. Figure 40 compares the characteristics of the DLL's output signals to those of the CLKIN signal. The CLK2X output generates a 25% duty cycle clock at the same frequency as the CLKIN signal until the DLL has achieved lock. The duty cycle of the CLKDV outputs may differ somewhat from 50% (i.e., the signal is High for less than 50% of the period) when the CLKDV_DIVIDE attribute is set to a non-integer value and the DLL is operating in the High Frequency mode.
Phase:
0
90 180 270
0
90 180 270
0
Input Signal (30% Duty Cycle)
t
CLKIN
Output Signal - Duty Cycle is Always Corrected
CLK2X
CLK2X180 (1) CLKDV
Digital Frequency Synthesizer (DFS)
The DFS component generates clock signals the frequency of which is a product of the clock frequency at the CLKIN input and a ratio of two user-determined integers. Because of the wide range of possible output frequencies such a ratio permits, the DFS feature provides still further flexibility than the DLL's basic synthesis options as described in the preceding section. The DFS component's two dedicated outputs, CLKFX and CLKFX180, are defined in Table 28. The signal at the CLKFX180 output is essentially an inversion of the CLKFX signal. These two outputs always exhibit a 50% duty cycle. This is true even when the CLKIN signal does not. These DFS clock outputs are driven at the same time as the DLL's seven clock outputs. The numerator of the ratio is the integer value assigned to the attribute CLKFX_MULTIPLY and the denominator is the integer value assigned to the attribute CLKFX_DIVIDE. These attributes are described in Table 27. The output frequency (fCLKFX) can be expressed as a function of the incoming clock frequency (fCLKIN) as follows: fCLKFX = fCLKIN*(CLKFX_MULTIPLY/CLKFX_DIVIDE) (3) Regarding the two attributes, it is possible to assign any combination of integer values, provided that two conditions are met: 1. The two values fall within their corresponding ranges, as specified in Table 27.
Output Signal - Attribute Corrects Duty Cycle
DUTY_CYCLE_CORRECTION = FALSE CLK0
CLK90
CLK180
CLK270 DUTY_CYCLE_CORRECTION = TRUE CLK0
CLK90
CLK180
CLK270
DS099-2_10_031303
Figure 40: Characteristics of the DLL Clock Outputs
DFS With or Without the DLL
The DFS component can be used with or without the DLL component: Without the DLL, the DFS component multiplies or divides the CLKIN signal frequency according to the respective CLKFX_MULTIPLY and CLKFX_DIVIDE values,
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Functional Description generating a clock with the new target frequency on the CLKFX and CLKFX180 outputs. Though classified as belonging to the DLL component, the CLKIN input is shared with the DFS component. This case does not employ feedback loop. Therefore, it cannot correct for clock distribution delay. With the DLL, the DFS operates as described in the preceding case, only with the additional benefit of eliminating the clock distribution delay. In this case, a feedback loop from the CLK0 output to the CLKFB input must be present. The DLL and DFS components work together to achieve this phase correction as follows: Given values for the CLKFX_MULTIPLY and CLKFX_DIVIDE attributes, the DLL selects the delay element for which the output clock edge coincides with the input clock edge whenever mathematically possible. For example, when CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, the input and output clock edges coincide every three input periods, which is equivalent in time to five output periods. Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values achieve faster lock times. With no factors common to the two attributes, alignment occurs once with every number of cycles equal to the CLKFX_DIVIDE value. Therefore, it is recommended that the user reduce these values by factoring wherever possible. For example, given CLKFX_MULTIPLY = 9 and CLKFX_DIVIDE = 6, removing a factor of three yields CLKFX_MULTIPLY = 3 and CLKFX_DIVIDE = 2. While both value-pairs result in the multiplication of clock frequency by 3/2, the latter value-pair enables the DLL to lock more quickly.
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DFS Clock Output Connections
There are two basic cases that determine how to connect the DFS clock outputs: on-chip and off-chip, which are illustrated in Figure 39a and Figure 39c, respectively. This is similar to what has already been described for the DLL component. See DLL Clock Output and Feedback Connections. In the on-chip case, it is possible to connect either of the DFS's two output clock signals through general routing resources to the FPGA's internal registers. Either a Global Clock Buffer (BUFG) or a BUFGMUX affords access to the global clock network. The optional feedback loop is formed in this way, routing CLK0 to a global clock net, which in turn drives the CLKFB input. In the off-chip case, the DFS's two output clock signals, plus CLK0 for an optional feedback loop, can exit the FPGA using output buffers (OBUF) to drive a clock network plus registers on the board. The feedback loop is formed by feeding the CLK0 signal back into the FPGA using an IBUFG, which directly accesses the global clock network, or an IBUF. Then the global clock net is connected directly to the CLKFB input.
Phase Shifter (PS)
The DCM provides two approaches to controlling the phase of a DCM clock output signal relative to the CLKIN signal: First, there are nine clock outputs that employ the DLL to achieve a desired phase relationship: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV CLKFX, and CLKFX180. These outputs afford "coarse" phase control. The second approach uses the PS component described in this section to provide a still finer degree of control. The PS component accomplishes this by introducing a "fine phase shift" (TPS) between the CLKFB and CLKIN signals inside the DLL component. The user can control this fine phase shift down to a resolution of 1/512 of a CLKIN cycle or one tap delay (DCM_TAP), whichever is greater. When in use, the PS component shifts the phase of all nine DCM clock output signals together. If the PS component is used together with a DCM clock output such as the CLK90, CLK180, CLK270, CLK2X180, and CLKFX180, then the fine phase shift of the former gets added to the coarse phase shift of the latter.
Table 27: DFS Attributes
Attribute CLKFX_MULTIPLY Description Frequency multiplier constant Frequency divisor constant Values Integer from 2 to 32, inclusive Integer from 1 to 32, inclusive
CLKFX_DIVIDE
Table 28: DFS Signals
Signal CLKFX Direction Output Description Multiplies the CLKIN frequency by the attribute-value ratio (CLKFX_MULTIPLY/ CLKFX_DIVIDE) to generate a clock signal with a new target frequency. Generates a clock signal with same frequency as CLKFX, only shifted 180 out-of-phase.
PS Component Enabling and Mode Selection
The CLKOUT_PHASE_SHIFT attribute enables the PS component for use in addition to selecting between two operating modes. As described in Table 29, this attribute has three possible values: NONE, FIXED, and VARIABLE. When CLKOUT_PHASE_SHIFT is set to NONE, the PS component is disabled and its inputs, PSEN, PSCLK, and PSINCDEC, must be tied to GND. The set of waveforms in Figure 41a shows the disabled case, where the DLL maintains a zero-phase alignment of signals CLKFB and CLKIN upon which the PS component has no effect. The PS comDS312-2 (v1.1) March 21, 2005 Advance Product Specification
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Output
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Functional Description mode and the Variable Phase mode, respectively. These two modes are described in the sections that follow.
ponent is enabled by setting the attribute to either the FIXED or VARIABLE values, which select the Fixed Phase
Table 29: PS Attributes
Attribute CLKOUT_PHASE_SHIFT PHASE_SHIFT Description Disables the PS component or chooses between Fixed Phase and Variable Phase modes. Determines size and direction of initial fine phase shift. Values NONE, FIXED, VARIABLE Integers from -255 to +255
Determining the Fine Phase Shift
The user controls the phase shift of CLKFB relative to CLKIN by setting and/or adjusting the value of the PHASE_SHIFT attribute. This value must be an integer ranging from -255 to +255. This corresponds to a phase shift range of -180 to +180 degrees, which is different from the original Spartan-3 DCM. The PS component uses this value to calculate the desired fine phase shift (TPS) as a fraction of the CLKIN period (TCLKIN). Given values for PHASE_SHIFT and TCLKIN, it is possible to calculate TPS as follows: TPS = (PHASE_SHIFT/512) * TCLKIN (4) Both the Fixed Phase and Variable Phase operating modes employ this calculation. If the PHASE_SHIFT value is zero, then CLKFB and CLKIN are in phase, the same as when the PS component is disabled. When the PHASE_SHIFT value is positive, the CLKFB signal is shifted later in time with respect to CLKIN. If the attribute value is negative, the CLKFB signal is shifted earlier in time with respect to CLKIN.
The Fixed Phase Mode
This mode fixes the desired fine phase shift to a fraction of the TCLKIN, as determined by Equation (4) and its user-selected PHASE_SHIFT value P. The set of waveforms in Figure 41b illustrates the relationship between CLKFB and CLKIN in the Fixed Phase mode. In the Fixed Phase mode, the PSEN, PSCLK, and PSINCDEC inputs are not used and must be tied to GND. In Figure 41: * P represents the integer value ranging from -255 to +255 to which the PHASE_SHIFT attribute is assigned. (P = approximately -90 as shown) N is an integer value ranging from (P - 255) to (+255 - P) that represents the net phase shift effect from a series of increment and/or decrement operations. N = {Total number of increments} - {Total number of decrements} provided the user does not try to increment past + 255 or decrement past -255. A positive value for N indicates a net increment; a negative value indicates a net decrement.
*
*
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Functional Description
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a. CLKOUT_PHASE_SHIFT = NONE
CLKIN
CLKFB
b. CLKOUT_PHASE_SHIFT = FIXED
CLKIN Shift Range over all P Values:
-255 0 +255 P 512 * TCLKIN
CLKFB
c. CLKOUT_PHASE_SHIFT = VARIABLE
CLKIN Shift Range over all P Values:
-255 0 +255 P * TCLKIN 512
CLKFB before Increment Shift Range over all N Values:
N *T 512 CLKIN
CLKFB after Increment
DS312-2_61_021505
Figure 41: Phase Shifter Waveforms
The Variable Phase Mode
The Variable Phase mode dynamically adjusts the fine phase shift over time using three inputs to the PS compo-
nent (PSEN, PSCLK, and PSINCDEC), as defined in Table 30.
Table 30: Signals for Variable Phase Mode
Signal PSEN(1) PSCLK(1) PSINCDEC(1) PSDONE
Notes:
1. It is possible to program this input for either a true or inverted polarity.
Direction Input Input Input Output
Description Enables PSCLK for variable phase adjustment. Clock to synchronize phase shift adjustment. Chooses between increment and decrement for phase adjustment. It is synchronized to the PSCLK signal. Goes High to indicate that present phase adjustment is complete and PS component is ready for next phase adjustment request. It is synchronized to the PSCLK signal.
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Functional Description Asserting the Reset (RST) input, returns TPS to its original shift time, as determined by the PHASE_SHIFT attribute value. The set of waveforms in Figure 41c illustrates the relationship between CLKFB and CLKIN in the Variable Phase mode.
Just following device configuration, the PS component initially determines TPS by evaluating Equation (4) for the value assigned to the PHASE_SHIFT attribute. Then to dynamically adjust that phase shift, use the three PS inputs to increase or decrease the fine phase shift. PSINCDEC is synchronized to the PSCLK clock signal, which is enabled by asserting PSEN. It is possible to drive the PSCLK input with the CLKIN signal or any other clock signal. A request for phase adjustment is entered as follows: For each PSCLK cycle that PSINCDEC is High, the PS component adds 1/512 of a CLKIN cycle to TPS. Similarly, for each enabled PSCLK cycle that PSINCDEC is Low, the PS component subtracts 1/512 of a CLKIN cycle from TPS. The phase adjustment may require as many as 100 CLKIN cycles plus three PSCLK cycles to take effect, at which point the output PSDONE goes High for one PSCLK cycle. This pulse indicates that the PS component has finished the present adjustment and is now ready for the next request.
The Status Logic Component
The Status Logic component not only reports on the state of the DCM but also provides a means of resetting the DCM to an initial known state. The signals associated with the Status Logic component are described in Table 31. As a rule, the Reset (RST) input is asserted only upon configuring the device or changing the CLKIN frequency. A DCM reset does not affect attribute values (e.g., CLKFX_MULTIPLY and CLKFX_DIVIDE). If not used, tie RST to GND. The eight bits of the STATUS bus are defined in Table 32.
Table 31: Status Logic Signals
Signal RST STATUS[7:0] LOCKED Direction Input Output Output Description A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for a delay of zero. Sets the LOCKED output Low. This input is asynchronous. The bit values on the STATUS bus provide information regarding the state of DLL and PS operation Indicates that the CLKIN and CLKFB signals are in phase by going High. The two signals are out-of-phase when Low.
Table 32: DCM Status Bus
Bit 0 1 2 3-6
Notes:
1. If only the DFS clock outputs are used, but none of the DLL clock outputs, this bit does not go High when the CLKIN signal stops.
Name Reserved CLKIN Stopped CLKFX Stopped Reserved -
Description
A value of 1 indicates that the CLKIN input signal is not toggling. A value of 0 indicates toggling. This bit functions only when the CLKFB input is connected.(1) A value of 1 indicates that the CLKFX output is not toggling. A value of 0 indicates toggling. This bit functions only when the CLKFX or CLKFX180 output are connected. -
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Functional Description
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Stabilizing DCM Clocks Before User Mode
The STARTUP_WAIT attribute shown in Table 33 optionally delays the end of the FPGA's configuration process until after the DCM locks to the incoming clock frequency. This option ensures that the FPGA remains in the Startup phase of configuration until all clock outputs generated by the DCM are stable. When all the DCMs with their STARTUP_WAIT attribute set to TRUE assert the LOCKED signal, then the FPGA completes its configuration process and proceeds to user mode. The associated bitstream generator (BitGen) option LCK_cycle specifies one of the six cycles in the Startup phase. The selected cycle defines the point at which configuration halts until the all the LOCKED outputs go High. Also see Start-Up, page 91.
Clock Buffers/Multiplexers
Clock Buffers/Multiplexers either drive clock input signals directly onto a clock line (BUFG) or optionally provide a multiplexer to switch between two unrelated, possibly asynchronous clock signals (BUFGMUX). Each BUFGMUX element, shown in Figure 43, is a 2-to-1 multiplexer. The select line, S, chooses which of the two inputs, I0 or I1, drives the BUFGMUX's output signal, O, as described in Table 34. The switching from one clock to the other is glitch-less, and done in such a way that the output High and Low times are never shorter than the shortest High or Low time of either input clock.
Table 34: BUFGMUX Select Mechanism
S Input O Output I0 Input I1 Input
Table 33: STARTUP_WAIT Attribute
Attribute STARTUP_WAIT Description Delays transition from configuration to user mode until DCM locks to input clock. Values TRUE, FALSE
0 1
Clocking Infrastructure
The Spartan-3E clocking infrastructure, shown in Figure 42, provides a series of low-capacitance, low-skew interconnect lines well-suited to carrying high-frequency signals throughout the FPGA. The infrastructure also includes the clock inputs and BUFGMUX clock buffers/multiplexers. The Xilinx Place-and-Route (PAR) software automatically routes high-fanout clock signals using these resources.
The BUFG clock buffer primitive drives a single clock signal onto the clock network and is essentially the same element as a BUFGMUX, just without the clock select mechanism. Similarly, the BUFGCE primitive creates an enabled clock buffer using the BUFGMUX select mechanism. The I0 and I1 inputs to an BUFGMUX element originate from clock input pins, DCMs, or Double-Line interconnect, as shown in Figure 43. As shown in Figure 42, there are 24 BUFGMUX elements distributed around the four edges of the device. Clock signals from the four BUFGMUX elements at the top edge and the four at the bottom edge are truly global and connect to all clocking quadrants. The eight left-edge BUFGMUX elements only connect to the two clock quadrants in the left half of the device. Similarly, the eight right-edge BUFGMUX elements only connect to the right half of the device. BUFGMUX elements are organized in pairs and share I0 and I1 connections with adjacent BUFGMUX elements from a common clock switch matrix as shown in Figure 43. For example, the input on I0 of one BUFGMUX also a shared input to I1 of the adjacent BUFGMUX. The clock switch matrix for the left- and right-edge BUFGMUX elements receive signals from any of the three following sources: an LHCLK or RHCLK pin as appropriate, a Double-Line interconnect, or a DCM in the XC3S1200E and XC3S1600E devices. By contrast, the clock switch matrixes on the top and bottom edges receive signals from any of the five following sources: two GCLK pins, two DCM outputs, or one Double-Line interconnect. Table 36 indicates permissible connections between clock inputs and BUFGMUX elements. The four BUFGMUX elements on the top edge are paired together and share inputs from the eight global clock inputs along the top edge. Each
Clock Inputs
Clock pins accept external clock signals and connect directly to DCMs and BUFGMUX elements. Each Spartan-3E FPGA has: * * * 16 Global Clock inputs (GCLK0 through GCLK15) located along the top and bottom edges of the FPGA 8 Right-Half Clock inputs (RHCLK0 through RHCLK7) located along the right edge 8 Left-Half Clock inputs (LHCLK0 through LHCLK7) located along the left edge
Clock inputs optionally connect directly to DCMs using dedicated connections. Table 35 shows the clock inputs that feed a specific DCM within a given Spartan-3E part number. Different Spartan-3E FPGA densities have different numbers of DCMs. Each clock input is also optionally a user-I/O pin and connects to internal interconnect. Some clock pad pins are input-only pins as indicated in Module 4 of the Spartan-3E Data Sheet.
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Functional Description The connections for the bottom-edge BUFGMUX elements is similar to the top-edge connections. On the left and right edges, only two clock inputs feed each pair of BUFGMUX elements.
BUFGMUX pair connects to four of the eight global clock inputs, as shown in Figure 42. This optionally allows differential inputs to the global clock inputs without wasting a BUFGMUX element.
Global Clock Inputs
GCLK11 GCLK7 GCLK9 GCLK5 GCLK8 GCLK4 GCLK10 GCLK6
BUFGMUX pair BUFGMUX
LHCLK1 LHCLK0
DCM
XC3S250E (X0Y1) XC3S500E (X0Y1) XC3S1200E (X1Y3) XC3S1600E (X1Y3)
DCM
4 4 H G F E
X1Y10 X1Y11 X2Y10 X2Y11
4 4
X0Y9
H
XC3S100E (X0Y1) XC3S250E (X1Y1) XC3S500E (X1Y1) XC3S1200E (X2Y3) XC3S1600E (X2Y3)
Clock Line in Quadrant
RHCLK7 RHCLK6
H
X3Y9 X3Y8
X0Y8
Top Left Quadrant (TL) G 4 4 Top Spine
Top Right Quadrant (TR)
4
*
8
*
8
G 4
4
DCM
XC3S1200E (X0Y2) XC3S1600E (X0Y2)
DCM
XC3S1200E (X3Y2) XC3S1600E (X3Y2)
4
LHCLK3 LHCLK2
* *
* *
4 F
4 F
4
RHCLK5 RHCLK4 RHCLK3 RHCLK2
X3Y7
Left-Half Clock Inputs
X0Y6 X0Y7
Right-Half Clock Inputs
X3Y6
E Left Spine D
LHCLK5 LHCLK4
8
Figure 44a Figure 44a
8
Horizontal
Spine
8
Figure 44b Figure 44b
8
E Right Spine D
X0Y5
X3Y5 X3Y4
X0Y4
C 4
*
8 Bottom Spine
*
8
4
C 4
4
DCM
XC3S1200E (X0Y1) XC3S1600E (X0Y1)
* *
4 Bottom Left Quadrant (BL)
* *
Bottom Right Quadrant (BR)
DCM
XC3S1200E (X3Y1) XC3S1600E (X3Y1)
4
LHCLK7 LHCLK6
4 B
4 B
4
RHCLK1 RHCLK0
X3Y3
X0Y2 X0Y3
X3Y2
A
A
DCM
XC3S250E (X0Y0) XC3S500E (X0Y0) XC3S1200E (X1Y0) XC3S1600E (X1Y0)
4 4
D
C
B
A 4
4
DCM
XC3S100E (X0Y0) XC3S250E (X1Y0) XC3S500E (X1Y0) XC3S1200E (X2Y0) XC3S1600E (X2Y0)
X1Y0 X1Y1
X2Y0 X2Y1
GCLK2 GCLK14
GCLK0 GCLK12 GCLK1 GCLK13
DS312-2_04_030205
GCLK3 GCLK15
Global Clock Inputs
Notes:
1. 2. Number of DCMs and locations of these DCM varies for different device densities. The left and right DCMs are only in the XC3S1200E and XC3S1600E. The XC3S100E has only two DCMs, one on the top right and one on the bottom right of the die.
Figure 42: Spartan-3E Internal Quadrant-Based Clock Network (Top View)
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Functional Description
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Table 35: Direct Connections from Clock Inputs to DCMs and Associated DCM Location String
Clock Input GCLK[3:0] RHCLK[3:0] RHCLK[7:4] GCLK[7:4] GCLK[11:8] LHCLK[3:0] LHCLK[7:4] GCLK[15:12] XC3S100E DCM_X0Y0 N/A N/A DCM_X0Y1 N/A N/A N/A N/A XC3S250E/XC3S500E DCM_X1Y0 N/A N/A DCM_X1Y1 DCM_X0Y1 N/A N/A DCM_X0Y0 XC3S1200E/XC3S1600E DCM_X2Y0 DCM_X3Y1 DCM_X3Y2 DCM_X2Y2 DCM_X1Y3 DCM_X0Y2 DCM_X0Y1 DCM_X1Y0
Table 36: Connections from Clock Inputs to BUFGMUX Elements and Associated Quadrant Clock
Quadrant Clock Line(1) A B C D E F G H
Notes:
1. 2. See Quadrant Clock Routing for connectivity details for the eight quadrant clocks. See Figure 42 for specific BUFGMUX locations and Figure 44 for information on how BUFGMUX elements drive onto a specific clock line within a quadrant.
Left-Half BUFGMUX
Location(2) I0 Input I1 Input
Top or Bottom BUFGMUX
Location(2) I0 Input I1 Input
Right-Half BUFGMUX
Location(2) I0 Input I1 Input
X0Y2 X0Y3 X0Y4 X0Y5 X0Y6 X0Y7 X0Y8 X0Y9
LHCLK7 LHCLK6 LHCLK5 LHCLK4 LHCLK3 LHCLK2 LHCLK1 LHCLK0
LHCLK6 LHCLK7 LHCLK4 LHCLK5 LHCLK2 LHCLK3 LHCLK0 LHCLK1
X2Y1 X2Y0 X1Y1 X1Y0 X2Y11 X2Y10 X1Y11 X1Y10
GCLK0 or GCLK12 GCLK1 or GCLK13 GCLK2 or GCLK14 GCLK3 or GCLK15 GCLK4 or GCLK8 GCLK5 or GCLK9 GCLK6 or GCLK10 GCLK7 or GCLK11
GCLK1 or GCLK13 GCLK0 or GCLK12 GCLK3 or GCLK15 GCLK2 or GCLK14 GCLK5 or GCLK9 GCLK4 or GCLK8 GCLK7 or GCLK11 GCLK6 or GCLK10
X3Y2 X3Y3 X3Y4 X3Y5 X3Y6 X3Y7 X3Y8 X3Y9
RHCLK0 RHCLK1 RHCLK2 RHCLK3 RHCLK4 RHCLK5 RHCLK6 RHCLK7
RHCLK1 RHCLK0 RHCLK3 RHCLK2 RHCLK5 RHCLK4 RHCLK7 RHCLK6
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Functional Description
Left-/Right-Half BUFGMUX CLK Switch Matrix BUFGMUX S I0 I1
Top/Bottom (Global) BUFGMUX CLK Switch Matrix BUFGMUX S I0 I1 I0 I1 S
0O 1
0O 1 0O 1
I0 0 O I1 1 S LHCLK or RHCLK input Double Line DCM output* *(XC3S1200E and and XC3S1600E only)
1st GCLK pin 1st DCM output Double Line 2nd DCM output 2nd GCLK pin
DS312-2_16_022505
Figure 43: Clock Switch Matrix to BUFGMUX Pair Connectivity
Quadrant Clock Routing
The clock routing within the FPGA is quadrant-based, as shown in Figure 42. Each clock quadrant supports eight total clock signals, labeled `A' through `H' in Table 36 and Figure 44. The clock source for an individual clock line originates either from a global BUFGMUX element along the top and bottom edges or from a BUFGMUX element along the associated edge, as shown in Figure 44. The clock lines feed the synchronous resource elements (CLBs, IOBs, block RAM, multipliers, and DCMs) within the quadrant.
The four quadrants of the device are: * * * * Top Right (TR) Bottom Right (BR) Bottom Left (BL) Top Left (TL)
Note that the quadrant clock notation (TR, BR, BL, TL) is separate from that used for similar IOB placement constraints.
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BUFGMUX Output X2Y1 (Global) X0Y2 (Left Half) X2Y0 (Global) X0Y3 (Left Half) X1Y1 (Global) X0Y4 (Left Half) X1Y0 (Global) X0Y5 (Left Half) X2Y11 (Global) X0Y6 (Left Half) X2Y10 (Global) X0Y7 (Left Half) X1Y11 (Global) X0Y8 (Left Half) X1Y10 (Global) X0Y9 (Left Half)
Clock Line
BUFGMUX Output X2Y1 (Global) X3Y2 (Right Half) X2Y0 (Global) X3Y3 (Right Half) X1Y1 (Global) X3Y4 (Right Half) X1Y0 (Global) X3Y5 (Right Half) X2Y11 (Global) X3Y6 (Right Half) X2Y10 (Global) X3Y7 (Right Half) X1Y11 (Global) X3Y8 (Right Half) X1Y10 (Global) X3Y9 (Right Half)
Clock Line
A B C D E F G H
A B C D E F G H
a. Left (TL and BL Quadrants) Half of Die
b. Right (TR and BR Quadrants) Half of Die
DS312-2_17_030105
Figure 44: Clock Sources for the Eight Clock Lines within a Clock Quadrant
The outputs of the top or bottom BUFGMUX elements connect to two vertical spines, each comprising four vertical clock lines as shown in Figure 42. At the center of the die, these clock signals connect to the eight-line horizontal clock spine. Outputs of the left and right BUFGMUX elements are routed onto the left or right horizontal spines, each comprising eight horizontal clock lines. Each of the eight clock signals in a clock quadrant derives either from a global clock signal or a half clock signal. In other words, there are up to 24 total potential clock inputs to the FPGA, eight of which can connect to clocked elements in a single clock quadrant. Figure 44 shows how the clock lines in each quadrant are selected from associated BUFGMUX sources. For example, if quadrant clock `A' in the bottom left (BL) quadrant originates from BUFGMUX_X2Y1, then the clock signal from BUFGMUX_X0Y2 is unavailable in the bottom left quadrant. However, the top left (TL) quadrant clock `A' can still solely use the output from either BUFGMUX_X2Y1 or BUFGMUX_X0Y2 as the source. To minimize the dynamic power dissipation of the clock network, the Xilinx development software automatically disables all clock segments not in use.
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Functional Description The switch matrix connects to the different kinds of interconnects across the device. An interconnect tile, shown in Figure 45, is defined as a single switch matrix connected to a functional element, such as a CLB, IOB, or DCM. If a functional element spans across multiple switch matrices such as the block RAM or multipliers, then an interconnect tile is defined by the number of switch matrices connected to that functional element. A Spartan-3E device can be represented as an array of interconnect tiles where interconnect resources are for the channel between any two adjacent interconnect tile rows or columns as shown in Figure 46.
Interconnect
Interconnect is the programmable network of signal pathways between the inputs and outputs of functional elements within the FPGA, such as IOBs, CLBs, DCMs, block RAM, etc. Interconnect, also called routing, is segmented for optimal connectivity. Functionally, interconnect resources are identical to that of the Spartan-3 architecture. There are four kinds of interconnects: long lines, hex lines, double lines, and direct lines. The Xilinx Place and Route (PAR) software exploits the rich interconnect array to deliver optimal system performance and the fastest compile times.
Switch Matrix
CLB
Switch Matrix Switch Matrix
Switch Matrix
IOB Switch Matrix
18Kb Block RAM
MULT 18 x 18
Switch Matrix
DCM
Switch Matrix
DS312_08_020905
Figure 45: Four Types of Interconnect Tiles (CLBs, IOBs, DCMs, and Block RAM/Multiplier)
Switch Matrix
IOB
Switch Matrix
IOB
Switch Matrix
IOB
Switch Matrix
IOB
Switch Matrix
Switch Matrix
IOB
Switch Matrix
CLB
Switch Matrix
CLB
Switch Matrix
CLB
Switch Matrix
Switch Matrix
IOB
Switch Matrix
CLB
Switch Matrix
CLB
Switch Matrix
CLB
Switch Matrix
Switch Matrix
IOB
Switch Matrix
CLB
Switch Matrix
CLB
Switch Matrix
CLB
Switch Matrix
Switch Matrix
IOB
Switch Matrix
CLB
Switch Matrix
CLB
Switch Matrix
CLB
Switch Matrix
DS312_09_020905
Figure 46: Array of Interconnect Tiles in Spartan-3E FPGA
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Functional Description There are four type of general-purpose interconnect available in each channel, as shown in Figure 47 and described below.
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Global Controls (STARTUP_SPARTAN3E)
In addition to the general-purpose interconnect, Spartan-3E FPGAs have two global logic control signals, as described in Table 37. These signals are available to the FPGA application via the STARTUP_SPARTAN3E primitive.
Long Lines
Each set of 24 long line signals spans the die both horizontally and vertically and connects to one out of every six interconnect tiles. At any tile, four of the long lines drive or receive signals from a switch matrix. Because of their low capacitance, these lines are well-suited for carrying high-frequency signals with minimal loading effects (e.g. skew). If all global clock lines are already committed and additional clock signals remain to be assigned, long lines serve as a good alternative.
Table 37: Spartan-3E Global Logic Control Signals
Global Control Input Description When driven High, asynchronously places all registers and flip-flops in their initial state (see Initialization, page 24). Asserted automatically during the FPGA configuration process (see Start-Up, page 91). When driven High, asynchronously forces all I/O pins to a high-impedance state (Hi-Z, three-state).
GSR
Hex Lines
Each set of eight hex lines are connected to one out of every three tiles, both horizontally and vertically. Thirty-two hex lines are available between any given interconnect tile. Hex lines are only driven from one end of the route. GTS
Double Lines
Each set of eight double lines are connected to every other tile, both horizontally and vertically. in all four directions. Thirty-two double lines available between any given interconnect tile. Double lines are more connections and more flexibility, compared to long line and hex lines.
The Global Set/Reset (GSR) signal replaces the global reset signal included in many ASIC-style designs. Use the GSR control instead of a separate global reset signal in the design to free up CLB inputs, resulting in a smaller, more efficient design. Similarly, the GSR signal is asserted automatically during the FPGA configuration process, guaranteeing that the FPGA starts-up in a known state. The STARTUP_SPARTAN3E primitive also includes two other signals used specifically during configuration. The MBT signals are for Dynamically Loading Multiple Configuration Images Using MultiBoot Option, page 78. The CLK input is an alternate clock for configuration Start-Up, page 91.
24
Direct Connections
Direct connect lines route signals to neighboring tiles: vertically, horizontally, and diagonally. These lines most often drive a signal from a "source" tile to a double, hex, or long line and conversely from the longer interconnect back to a direct line accessing a "destination" tile. Horizontal and Vertical Long Lines (horizontal channel shown as an example)
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
* * *
* * *
* * *
* * *
6
6 8
6
6
DS312-2_10_022305
Horizontal and Vertical Hex Lines (horizontal channel shown as an example)
CLB
CLB
CLB
CLB
CLB
CLB
DS312-2_11_020905
Figure 47: Interconnect Types between Two Adjacent Interconnect Tiles
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* * * 6
CLB
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Functional Description
Horizontal and Vertical Double Lines (horizontal channel shown as an example) Direct Connections
8
CLB
CLB
CLB
DS312-2_15_022305
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
DS312-2_12_020905
Figure 47: Interconnect Types between Two Adjacent Interconnect Tiles
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Functional Description
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Configuration
Differences from Spartan-3 FPGAs
In general, Spartan-3E FPGA configuration modes are a superset to those available in Spartan-3 FPGAs. Two new modes added in Spartan-3E FPGAs provide a glue-less configuration interface to industry-standard parallel NOR Flash and SPI serial Flash memories. Unlike Spartan-3 FPGAs, nearly all of the Spartan-3E configuration pins become available as user I/Os after configuration.
borrowed and returned to the application as general-purpose user I/Os after configuration completes. Spartan-3E FPGAs offer several configuration options to minimize the impact of configuration on the overall system design. In some configuration modes, the FPGA generates a clock and loads itself from an external memory source, either serially or via a byte-wide data path. Alternatively, an external host such as a microprocessor downloads the FPGA's configuration data using a simple synchronous serial interface or via a byte-wide peripheral-style interface. Furthermore, multiple-FPGA designs share a single configuration memory source, creating a structure called a daisy chain. Three FPGA pins--M2, M1, and M0--select the desired configuration mode. The mode pin settings appear in Table 38. The mode pin values are sampled during the start of configuration when the FPGA's INIT_B output goes High. After the FPGA completes configuration, the mode pins are available as user I/Os.
Configuration Process
The function of a Spartan-3E FPGA is defined by loading application-specific configuration data into the FPGA's internal, reprogrammable CMOS configuration latches (CCLs), similar to the way a microprocessor's function is defined by its application program. For FPGAs, this configuration process uses a subset of the device pins, some of which are dedicated to configuration; other pins are merely
Table 38: Spartan-3E Configuration Mode Pin Settings
Master Serial M[2:0] mode pin settings Data width Configuration memory source <0:0:0> SPI <0:0:1> BPI <0:1:0>=Up <0:1:1>=Down Byte-wide Industry-standard parallel NOR Flash Slave Parallel <1:1:0> Slave Serial <1:1:1> JTAG <1:0:1>
Serial Xilinx Platform Flash
Serial Industry-standard SPI Serial Flash
Byte-wide Any source via microcontroller, CPU, Xilinx parallel Platform Flash, etc. External clock on CCLK pin
Serial Any source via microcontroller, CPU, Xilinx Platform Flash, etc. External clock on CCLK pin
Serial Any source via microcontroller, CPU, etc. and System Ace CF
Clock source Total I/O pins borrowed during configuration Configuration mode for downstream daisy-chained FPGAs Self-configuring applications (no external download host) Uses low-cost, industry-standard Flash
Internal oscillator
Internal oscillator
Internal oscillator
External clock on TCK pin
8
Slave Serial
13
Slave Serial
46
Slave Parallel
21
Slave Parallel or Memory Mapped
Possible using XCFxxP Platform Flash, which optionally generates CCLK
8
Slave Serial
0
JTAG
Possible using XCFxxP Platform Flash, which optionally generates CCLK
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Functional Description
A specific Spartan-3E part type always requires a constant number of configuration bits, regardless of design complexity, as shown in Table 39. The configuration file size for a multiple-FPGA daisy-chain design equals the sum of the individual file sizes.
Pin Behavior During Configuration
Table 40 shows how various pins behave during the FPGA configuration process. The actual behavior depends on the values applied to the M2, M1, and M0 mode select pins and the HSWAP pin. The mode select pins determine which of the I/O pins are borrowed during configuration and how they function. In JTAG configuration mode, no user-I/O pins are borrowed for configuration. All I/O pins are high impedance (floating, three-stated, Hi-Z) during the configuration process. These pins are indicated in Table 40 as shaded table entries or cells. If the HSWAP input is Low, these pins have a pull-up resistor to their associated VCCO supply that is active throughout configuration. After configuration, pull-up and pull-down resistors are available in the FPGA application as described in Pull-Up and Pull-Down Resistors, page 9. Spartan-3E FPGAs have only six dedicated configuration pins, including the DONE and PROG_B pins, and the four JTAG boundary-scan pins: TDI, TDO, TMS, and TCK.
Table 39: Number of Bits to Program a Spartan-3E FPGA (Uncompressed Bitstreams)
Device XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E Number of Configuration Bits 581,344 1,352,192 2,267,136 3,832,320 5,957,760
Table 40: Pin Behavior during Configuration
Pin Name TDI TMS TCK TDO PROG_B DONE HSWAP M2 M1 M0 Master Serial TDI TMS TCK TDO PROG_B DONE HSWAP 0 0 0 SPI (Serial Flash) TDI TMS TCK TDO PROG_B DONE HSWAP 0 0 1 BPI (Parallel NOR Flash) TDI TMS TCK TDO PROG_B DONE HSWAP 0 1 0 = Up 1 = Down CCLK INIT_B CSO_B DOUT/BUSY MOSI/CSI_B D7 D6 D5 D4
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JTAG TDI TMS TCK TDO PROG_B DONE HSWAP 1 0 1
Slave Parallel TDI TMS TCK TDO PROG_B DONE HSWAP 1 1 0
Slave Serial TDI TMS TCK TDO PROG_B DONE HSWAP 1 1 1
Supply/ I/O Bank VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX 0 2 2 2
CCLK (O) INIT_B
CCLK (O) INIT_B CSO_B
CCLK (O) INIT_B CSO_B BUSY CSI_B D7 D6 D5 D4
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CCLK (I) INIT_B CSO_B BUSY CSI_B D7 D6 D5 D4
CCLK (I) INIT_B
2 2 2
DOUT
DOUT MOSI
DOUT
2 2 2 2 2 2
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Functional Description
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Table 40: Pin Behavior during Configuration (Continued)
Pin Name D3 D2 D1 D0/DIN RDWR_B A23 A22 A21 A20 A19/VS2 A18/VS1 A17/VS0 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 LDC0 LDC1 LDC2 HDC VS2 VS1 VS0 DIN DIN Master Serial SPI (Serial Flash) BPI (Parallel NOR Flash) D3 D2 D1 D0 RDWR_B A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 LDC0 LDC1 LDC2 HDC LDC0 LDC1 LDC2 HDC JTAG Slave Parallel D3 D2 D1 D0 RDWR_B DIN Slave Serial Supply/ I/O Bank 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Functional Description drive characteristics. For example, with VCCO = 3.3V, the output current when driving High, IOH, increases to approximately 12 to 16 mA, while the current when driving Low, IOL, remains 8 mA. At VCCO = 1.8V, the output current when driving High, IOH, decreases slightly to approximately 6 to 8 mA. Again, the current when driving Low, IOL, remains 8 mA.
Table 41 shows the default I/O standard setting for the various configuration pins during the configuration process. The configuration interface is designed primarily for 2.5V operation when the VCCO_2 (and VCCO_1 in BPI mode) connects to 2.5V. The configuration pins also operate at other voltages by setting VCCO_2 (and VCCO_1 in BPI mode) to either 3.3V or 1.8V. The change on the VCCO supply also changes the I/O
Table 41: Default I/O Standard Setting During Configuration (VCCO_2 = 2.5V)
Pin(s) All, including CCLK I/O Standard LVCMOS25 Output Drive 8 mA Slew Rate Slow
Master Serial Mode
In Master Serial mode (M[2:0] = <0:0:0>), the Spartan-3E FPGA configures itself from an attached Xilinx Platform Flash PROM, as illustrated in Figure 48. The FPGA supplies the CCLK output clock from its internal oscillator to the
+1.2V
attached Platform Flash PROM. In response, the Platform Flash PROM supplies bit-serial data to the FPGA's DIN input and the FPGA accepts this data on each rising CCLK edge.
Serial Master Mode `0' `0' `0'
M2 M1 M0
VCCO_2 DIN CCLK DOUT INIT_B
V
4.7k
P
VCCINT HSWAP VCCO_0
V
VCCO_0
XCFxxS = +3.3V XCFxxP = +1.8V VCCINT D0 CLK OE/RESET VCCO
V
+2.5V
4.7k
330
Spartan-3E
Platform Flash XCFxx
CE CEO VCCJ TDO +2.5V CF
+2.5V JTAG TDI TMS TCK TDO
TDI TMS TCK PROG_B GND
VCCAUX TDO
+2.5V TDI TMS TCK GND
DONE
PROG_B Recommend open-drain driver
DS312-2_44_021405
Figure 48: Master Serial Mode using Platform Flash PROM
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Functional Description The mode select pins, M[2:0], must all be Low when sampled, when the FPGA's INIT_B output goes High. After configuration, when the FPGA's DONE output goes High, the mode select pins are available as full-featured user-I/O pins.
P Similarly, the FPGA's HSWAP pin must be Low to enable pull-up resistors on all user-I/O pins during configuration or High to disable the pull-up resistors. The HSWAP control must remain at a constant logic level throughout
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FPGA configuration. After configuration, when the FPGA's DONE output goes High, the HSWAP pin is available as full-featured user-I/O pin and is powered by the VCCO_0 supply. The FPGA's DOUT pin is used in daisy-chain applications, described later. In a single-FPGA application, the FPGA's DOUT pin is not used but is actively driving during the configuration process.
Table 42: Serial Master Mode Connections
Pin Name HSWAP FPGA Direction Input Description User I/O Pull-Up Control. When Low during configuration, enables pull-up resistors in all I/O pins to respective I/O bank VCCO input. 0: Pull-ups during configuration 1: No pull-ups M[2:0] Input Mode Select. Selects the FPGA configuration mode. Serial Data Input. Configuration Clock. Generated by FPGA internal oscillator. Frequency controlled by ConfigRate bitstream generator option. If CCLK PCB trace is long or has multiple connections, terminate this output to maintain signal integrity. Serial Data Output. M2 = 0, M1 = 0, M0 = 0. Sampled when INIT_B goes High. Receives serial data from PROM's D0 output. Drives PROM's CLK clock input. User I/O During Configuration Drive at valid logic level throughout configuration. After Configuration User I/O
P
DIN CCLK
Input Output
User I/O User I/O
DOUT
Output
Actively drives. Not used in single-FPGA designs. In a daisy-chain configuration, this pin connects to DIN input of the next FPGA in the chain. Connects to PROM's OE/RESET input. FPGA clears PROM's address counter at start of configuration, enables outputs during configuration. PROM also holds FPGA in Initialization state until PROM reaches Power-On Reset (POR) state. If CRC error detected during configuration, FPGA drives INIT_B Low.
User I/O
INIT_B
Open-drain bidirectional I/O
Initialization Indicator. Active Low. Goes Low at start of configuration during Initialization memory clearing process. Released at end of memory clearing, when mode select pins are sampled. Requires external 4.7 k pull-up resistor to VCCO_2.
User I/O
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Functional Description
Table 42: Serial Master Mode Connections (Continued)
Pin Name DONE FPGA Direction Open-drain bidirectional I/O Description FPGA Configuration Done. Low during configuration. Goes High when FPGA successfully completes configuration. Requires external 330 pull-up resistor to 2.5V. During Configuration Connects to PROM's chip-enable (CE) input. Enables PROM during configuration. Disables PROM after configuration. After Configuration Pulled High via external pull-up. When High, indicates that the FPGA successfully configured. Drive PROG_B Low and release to reprogram FPGA.
PROG_B
Input
Program FPGA. Active Low. When asserted Low for 300 ns or longer, forces the FPGA to restart its configuration process by clearing configuration memory and resetting the DONE and INIT_B pins once PROG_B returns High. Requires external 4.7 k pull-up resistor to 2.5V. If driving externally, use an open-drain or open-collector driver.
Must be High during configuration to allow configuration to start. Connects to PROM's CF pin, allowing JTAG PROM programming algorithm to reprogram the FPGA.
Voltage Compatibility
The PROM's VCCINT supply must be either 3.3V for the serial XCFxxS Platform Flash PROMs or 1.8V for the serial/parallel XCFxxP PROMs.
V The FPGA's VCCO_2 supply input and the Platform Flash PROM's VCCO supply input must be the same voltage, ideally +2.5V. Both devices also support 1.8V and 3.3V interfaces but the FPGA's PROG_B and DONE pins require special attention as they are powered by the FPGA's VCCAUX supply, nominally 2.5V. See application note XAPP453: "The 3.3V Configuration of Spartan-3 FPGAs" for additional information.
The XC3S1600E requires an 8 Mbit PROM. There are two possible solutions. Either use a single 8 Mbit XCF08P parallel/serial PROM or cascade two 4 Mbit XCF04S serial PROMs. The two XCF04S PROMs use a 3.3V VCCINT supply while the XCF08P requires a 1.8V VCCINT supply. If the board does not already have a 1.8V supply available, the two cascaded XCF04S PROM solution is recommended.
CCLK Frequency
In Master Serial mode, the FPGA's internal oscillator generates the configuration clock frequency. The FPGA provides this clock on its CCLK output pin, driving the PROM's CLK input pin. The FPGA starts configuration at its lowest frequency and increases its frequency for the remainder of the configuration process if so specified in the configuration bitstream. The maximum frequency is specified using the ConfigRate bitstream generator option. Table 44 shows the maximum ConfigRate settings, approximately equal to MHz, for various Platform Flash devices and I/O voltages. For the serial XCFxxS PROMs, the maximum frequency also depends on the interface voltage.
Supported Platform Flash PROMs
Table 43 shows the smallest available Platform Flash PROM to program a single Spartan-3E FPGA. A multiple-FPGA daisy-chain application requires a Platform Flash PROM large enough to contain the sum of the various FPGA file sizes.
Table 43: Number of Bits to Program a Spartan-3E FPGA and Smallest Platform Flash PROM
Number of Configuration Bits 581,344 1,352,192 2,267,136 3,832,320 5,957,760 Smallest Available Platform Flash XCF01S XCF02S XCF04S XCF04S XCF08P or 2 x XCF04S
Table 44: Maximum ConfigRate Settings for Platform Flash
Platform Flash Part Number XCF01S XCF02S XCF04S XCF08P XCF16P XCF32P I/O Voltage (VCCO_2, VCCO) 3.3V or 2.5V 1.8V 3.3V, 2.5V, or 1.8V Maximum ConfigRate Setting 25 12 25
Device XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E
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Functional Description
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CCLK +1.2V XCFxxS = +3.3V XCFxxP = +1.8V VCCO_0 +1.2V
P
Serial Master Mode `0' `0' `0'
HSWAP
VCCINT VCCO_0 VCCO_2 DIN CCLK DOUT INIT_B
P
VCCINT D0 CLK OE/RESET VCCO
HSWAP
VCCINT VCCO_0 VCCO_2
VCCO_0
V
V
Slave Serial Mode `1' `1' `1' M2 M1 M0
V
M2 M1 M0
DOUT INIT_B
DOUT
Spartan-3E FPGA
+2.5V JTAG TDI TMS TCK TDO VCCAUX TDO +2.5V
Platform Flash XCFxx
CE CF CEO VCCJ TDO +2.5V TDI TMS TCK CCLK DIN
Spartan-3E FPGA
VCCAUX TDO +2.5V
TDI TMS TCK PROG_B GND
TDI TMS TCK GND
+2.5V
V
DONE
PROG_B
DONE GND
4.7k
PROG_B Recommend open-drain driver
4.7k
330
PROG_B TCK TMS DONE INIT_B
DS312-2_45_021405
Figure 49: Daisy-Chaining from Master Serial Mode
Daisy-Chaining
If the application requires multiple FPGAs with different configurations, then configure the FPGAs using a daisy chain, as shown in Figure 49. Use Master Serial mode (M[2:0] = <0:0:0>) for the FPGA connected to the Platform Flash PROM and Slave Serial mode (M[2:0] = <1:1:1>) for all other FPGAs in the daisy-chain. After the master FPGA--the FPGA on the left in the diagram--finishes loading its configuration data from the Platform Flash, the master device supplies data using its DOUT output pin to the next device in the daisy-chain, on the falling CCLK edge.
provided by the Xilinx iMPACT programming software and the associated Xilinx Parallel Cable IV, MultiPRO, or Platform Cable USB programming cables.
Storing Additional User Data in Platform Flash
After configuration, the FPGA application can continue to use the Master Serial interface pins to communicate with the Platform Flash PROM. If desired, use a larger Platform Flash PROM to hold additional non-volatile application data, such as MicroBlaze processor code, or other user data such as serial numbers and Ethernet MAC IDs. The FPGA first configures from Platform Flash PROM. Then using FPGA logic after configuration, the FPGA copies MicroBlaze code from Platform Flash into external DDR SDRAM for code execution. See XAPP694: "Reading User Data from Configuration PROMs" and XAPP482: "MicroBlaze Platform Flash/PROM Boot Loader and User Data Storage" for specific details on how to implement such an interface.
JTAG Interface
Both the Spartan-3E FPGA and the Platform Flash PROM have a four-wire IEEE 1149.1/1532 JTAG port. Both devices share the TCK clock input and the TMS mode select input. The devices may connect in either order on the JTAG chain with the TDO output of one device feeding the TDI input of the following device in the chain. The TDO output of the last device in the JTAG chain drives the JTAG connector. The JTAG interface on Spartan-3E FPGAs is powered by the 2.5V VCCAUX supply. Consequently, the PROM's VCCJ supply input must also be 2.5V. To create a 3.3V JTAG interface, please refer to application note XAPP453: "The 3.3V Configuration of Spartan-3 FPGAs" for additional information.
SPI Serial Flash Mode
In SPI Serial Flash mode (M[2:0] = <0:0:0>), the Spartan-3E FPGA configures itself from an attached industry-standard SPI serial Flash PROM, as illustrated in Figure 50 and Figure 52. The FPGA supplies the CCLK output clock from its internal oscillator to the clock input of the attached SPI Flash PROM.
In-System Programming Support
Both the FPGA and the Platform Flash PROM are in-system programmable via the JTAG chain. Download support is
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Functional Description
+1.2V
+3.3V
P
HSWAP
VCCO_0 +3.3V
SPI Mode `0' `0' `1' Variant Select `1' M2 M1 M0
VCCO_2 MOSI DIN CSO_B
I
4.7k
VCCINT VCCO_0
P
SPI Serial Flash
VCC DATA_IN DATA_OUT SELECT WR_PROTECT HOLD CLOCK GND
W
`1'
S
`1'
CCLK DOUT INIT_B VCCAUX TDO +2.5V
+2.5V JTAG TDI TMS TCK TDO
4.7k
+2.5V
VS2 VS1 VS0
Spartan-3E FPGA
+3.3V
PROG_B GND
DONE
PROG_B Recommend open-drain driver
4.7k
DS312-2_46_021405
Figure 50: SPI Flash PROM Interface for PROMs Supporting READ (0x03) and FAST_READ (0x0B)
S Although SPI is a standard four-wire interface, various
available SPI Flash PROMs use different command protocols. The FPGA's variant select pins, VS[2:0], define how the FPGA communicates with the SPI Flash, including which SPI Flash command the FPGA issues to start the read operation and the number of dummy bytes inserted before the FPGA expects to receive valid data from the SPI Flash. Table 45 shows the available SPI Flash PROMs expected to operate with Spartan-3E FPGAs. Other compatible devices might work but have not been tested for suitability with Spartan-3E FPGAs. All other VS[2:0] values are reserved for future use.
Figure 50 shows the general connection diagram for those SPI Flash PROMs that support the 0x03 READ command or the 0x0B FAST READ commands. Figure 51 shows the connection diagram for Atmel DataFlash serial PROMs, which also use an SPI-based protocol. Figure 54 demonstrates how to configure multiple FPGAs with different configurations, all stored in a single SPI Flash. The diagram uses standard SPI Flash memories but the same general technique applies for Atmel DataFlash.
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330
TDI TMS TCK
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Functional Description
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+1.2V
+3.3V
P
VCCO_0 +3.3V
SPI Mode `0' `0' `1' Variant Select `1' `1' `0' VS2 VS1 VS0 M2 M1 M0
VCCO_2 MOSI DIN CSO_B
I
4.7k
VCCINT HSWAP VCCO_0
P
Atmel AT45DB DataFlash
VCC SI SO CS WP RESET RDY/BUSY SCK GND +3.3V
W
`1'
Spartan-3E FPGA
CCLK DOUT INIT_B VCCAUX TDO +2.5V
Power-on monitor is only required if +3.3V (VCCO_2) supply is last supply in power-on sequence, after VCCINT and VCCAUX. Must delay FPGA configuration for > 20 ms after SPI DataFlash reaches its minimum VCC. Force FPGA INIT_B input or PROG_B input Low with an open-drain or opencollector driver.
+3.3V
4.7k
INIT_B
+2.5V
+2.5V JTAG TDI TMS TCK TDO
Power-On Monitor
4.7k
330
TDI TMS TCK PROG_B GND
or
+3.3V
DONE
PROG_B Recommend open-drain driver
PROG_B
Power-On Monitor
DS312-2_50a_022305
Figure 51: Atmel SPI-based DataFlash Configuration Interface
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Functional Description
Table 45: Variant Select Codes for SPI Serial Flash PROMs
VS2 VS1 VS0 SPI Read Command Dummy Bytes SPI Serial Flash Vendor STMicroelectronics (ST) NexFlash 1 1 1 FAST READ (0x0B) (see Figure 50) 1 Silicon Storage Technology (SST) Programmable Microelectronics Corp. (PMC) STMicroelectronics (ST) NexFlash 1 0 1 READ (0x03) (see Figure 50) 0 Silicon Storage Technology (SST) SPI Flash Family M25Pxx NX25Pxx SST25LFxxxA SST25VFxxxA Pm25LVxxx M25Pxx NX25Pxx SST25LFxxxA SST25VFxxxA SST25VFxxx Programmable Microelectronics Corp. (PMC) 1 1 Others 0 READ ARRAY (0xE8) (see Figure 51) Reserved are not used by the FPGA during configuration. However, the HOLD pin must be High during the configuration process. The PROM's write protect input must be High in order to write or program the Flash memory. 3 Atmel Corporation Pm25LVxxx AT45DB DataFlash
W Table 46 shows the connections between the SPI Flash PROM and the FPGA's SPI configuration interface. Each SPI Flash PROM vendor uses slightly different signal naming. The SPI Flash PROM's write protect and hold controls
Table 46: SPI Flash PROM Connections and Pin Naming
Silicon Storage Technology SI SO CE# SCK Atmel DataFlash SI SO CS SCK
SPI Flash Pin DATA_IN DATA_OUT SELECT CLOCK WR_PROTECT
W
FPGA Connection MOSI DIN CSO_B CCLK Not required for FPGA configuration. Must be High to program SPI Flash. Optional connection to FPGA user I/O after configuration. Not required for FPGA configuration but must be High during configuration. Optional connection to FPGA user I/O after configuration. Not applicable to Atmel DataFlash.
STMicro D Q S C
NexFlash DI DO CS CLK
W
WP
WP#
WP
HOLD (see Figure 50)
HOLD
HOLD
HOLD#
N/A
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Table 46: SPI Flash PROM Connections and Pin Naming (Continued)
Silicon Storage Technology Atmel DataFlash
SPI Flash Pin
FPGA Connection Only applicable to Atmel DataFlash. Not required for FPGA configuration but must be High during configuration. Optional connection to FPGA user I/O after configuration. Do not connect to FPGA's PROG_B as this will prevent direct programming of the DataFlash. Only applicable to Atmel DataFlash and only available on certain packages. Not required for FPGA configuration. Output from DataFlash PROM. Optional connection to FPGA user I/O after configuration.
STMicro
NexFlash
RESET (see Figure 51)
N/A
N/A
N/A
RESET
RDY/BUSY (see Figure 51)
N/A
N/A
N/A
RDY/BUSY
The mode select pins, M[2:0], and the variant select pins, VS[2:0] are sampled when the FPGA's INIT_B output goes High and must be at defined logic levels during this time. After configuration, when the FPGA's DONE output goes High, these pins are all available as full-featured user-I/O pins. Similarly, the FPGA's HSWAP pin must be Low to enable pull-up resistors on all user-I/O pins or High to disP
able the pull-up resistors. The HSWAP control must remain at a constant logic level throughout FPGA configuration. After configuration, when the FPGA's DONE output goes High, the HSWAP pin is available as full-featured user-I/O pin and is powered by the VCCO_0 supply. In a single-FPGA application, the FPGA's DOUT pin is not used but is actively driving during the configuration process.
Table 47: Serial Peripheral Interface (SPI) Connections
Pin Name HSWAP FPGA Direction Input Description User I/O Pull-Up Control. When Low during configuration, enables pull-up resistors in all I/O pins to respective I/O bank VCCO input. 0: Pull-ups during configuration 1: No pull-ups M[2:0] Input Mode Select. Selects the FPGA configuration mode. Variant Select. Instructs the FPGA how to communicate with the attached SPI Flash PROM. Serial Data Output. M2 = 0, M1 = 0, M0 = 1. Sampled when INIT_B goes High. Must be at the logic levels shown in Table 45. Sampled when INIT_B goes High. FPGA sends SPI Flash memory read commands and starting address to the PROM's serial data input. FPGA receives serial data from PROM's serial data output. User I/O During Configuration Drive at valid logic level throughout configuration. After Configuration User I/O
P
VS[2:0]
Input
User I/O
S
MOSI Output
User I/O
DIN
Input
Serial Data Input.
User I/O
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Functional Description
Table 47: Serial Peripheral Interface (SPI) Connections (Continued)
Pin Name CSO_B FPGA Direction Output Description Chip Select Output. Active Low. During Configuration Connects to the SPI Flash PROM's chip-select input. If HSWAP = 1, connect this signal to a 4.7 k pull-up resistor to 3.3V. After Configuration Drive CSO_B High after configuration to disable the SPI Flash and reclaim the MOSI, DIN, and CCLK pins. Optionally, re-use this pin and MOSI, DIN, and CCLK to continue communicating with SPI Flash. User I/O
CCLK
Output
Configuration Clock. Generated by FPGA internal oscillator. Frequency controlled by ConfigRate bitstream generator option. If CCLK PCB trace is long or has multiple connections, terminate this output to maintain signal integrity. Serial Data Output.
Drives PROM's clock input.
DOUT
Output
Actively drives. Not used in single-FPGA designs. In a daisy-chain configuration, this pin connects to DIN input of the next FPGA in the chain. Active during configuration. If SPI Flash PROM requires > 2 ms to awake after powering on, hold INIT_B Low until PROM is ready. If CRC error detected during configuration, FPGA drives INIT_B Low.
User I/O
INIT_B
Open-drain bidirectional I/O
Initialization Indicator. Active Low. Goes Low at start of configuration during Initialization memory clearing process. Released at end of memory clearing, when mode select pins are sampled. In daisy-chain applications, this signal requires an external 4.7 k pull-up resistor to VCCO_2. FPGA Configuration Done. Low during configuration. Goes High when FPGA successfully completes configuration. Requires external 330 pull-up resistor to 2.5V. Program FPGA. Active Low. When asserted Low for 300 ns or longer, forces the FPGA to restart its configuration process by clearing configuration memory and resetting the DONE and INIT_B pins once PROG_B returns High. Requires external 4.7 k pull-up resistor to 2.5V. If driving externally, use an open-drain or open-collector driver.
User I/O
DONE
Open-drain bidirectional I/O
Low indicates that the FPGA is not yet configured.
Pulled High via external pull-up. When High, indicates that the FPGA successfully configured.
PROG_B
Input
Must be High to allow configuration to start.
Drive PROG_B Low and release to reprogram FPGA. Hold PROG_B to force FPGA I/O pins into Hi-Z, allowing direct programming access to SPI Flash PROM pins.
Voltage Compatibility
Available SPI Flash PROMs use a single 3.3V supply voltage. All of the FPGA's SPI Flash interface signals are within
I/O Bank 2. Consequently, the FPGA's VCCO_2 supply voltage must also be 3.3V to match the SPI Flash PROM.
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Power-On Precautions if 3.3V Supply is Last in Sequence
Spartan-3E FPGAs have a built-in power-on reset (POR) circuit, as shown in Figure 63. The FPGA waits for its three power supplies -- VCCINT, VCCAUX, and VCCO to I/O Bank 2 (VCCO_2) -- to reach their respective power-on thresholds before beginning the configuration process.
The SPI Flash PROM is powered by the same voltage supply feeding the FPGA's VCCO_2 voltage input, typically 3.3V. SPI Flash PROMs specify that they cannot be accessed until their VCC supply reaches its minimum data sheet voltage, followed by an additional delay. For some devices, this additional delay is as little as 10 s as shown in Table 48. For other vendors, it is as much as 20 ms.
Table 48: Example Minimum Power-On to Select Times for Various SPI Flash PROMs
Vendor STMicroelectronics NexFlash Silicon Storage Technology Programmable Microelectronics Corporation Atmel Corporation SPI Flash PROM Part Number M25Pxx NX25xx SST25LFxx Pm25LVxxx AT45DBxx Data Sheet Minimum Time from VCC, min. to Select = Low Symbol TVSL TVSL TPU-READ TVCS Value 10 10 10 50 20 Units s s s s ms
In many systems, the 3.3V supply feeding the FPGA's VCCO_2 input is valid before the FPGA's other VCCINT and VCCAUX supplies, and consequently, there is no issue. However, if the 3.3V supply feeding the FPGA's VCCO_2 supply is last in the sequence, a potential race occurs between the FPGA and the SPI Flash PROM, as shown in Figure 52. If the FPGA's VCCINT and VCCAUX supplies are already valid, then the FPGA waits for VCCO_2 to reach its minimum threshold voltage before starting configuration. This threshold voltage is labeled as VCCO2T in Module 3 and ranges from approximately 0.4V to 1.0V, substantially lower than the SPI Flash PROM's minimum voltage. Once all three FPGA supplies reach their respective Power On Reset (POR) thresholds, the FPGA starts the configuration process and begins initializing its internal configuration memory. Initialization requires approximately 1 ms (TPOR,
3.3V Supply
minimum in Module 3), after which the FPGA deasserts INIT_B, selects the SPI Flash PROM, and starts sending the appropriate read command. The SPI Flash PROM must be ready for read operations at this time. If the 3.3V supply is last in the sequence and does not ramp fast enough, or if the SPI Flash PROM cannot be ready when required by the FPGA, delay the FPGA configuration process by holding either the FPGA's PROG_B input or INIT_B input Low, as highlighted in Figure 51. Release the FPGA when the SPI Flash PROM is ready. For example, a simple R-C delay circuit attached to the INIT_B pin forces the FPGA to wait for a preselected amount of time. Alternately, a Power Good signal from the 3.3V supply or a system reset signal accomplishes the same purpose. Use an open-drain or open-collector output when driving PROG_B or INIT_B.
SPI Flash cannot be selected SPI Flash PROM minimum voltage SPI Flash PROM CS delay (tVSL ) SPI Flash available for read operations SPI Flash PROM must be ready for FPGA access otherwise delay FPGA configuration FPGA accesses SPI Flash PROM
DS312-2_50b_022405
FPGA VCCO_2 minimum Power On Reset Voltage (VCCO2T )
(VCCINT, VCCAUX already valid)
FPGA initializes configuration memory (TPOR) Time
Figure 52: SPI Flash PROM/FPGA Power-On Timing if 3.3V Supply is Last in Power-On Sequence
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Functional Description ing for the SPI Flash device. Without examining the timing for a specific SPI Flash PROM, use ConfigRate = 12, which is approximately 12 MHz. SPI Flash PROMs that support the FAST READ command support higher data rates. Some such PROMs support up to ConfigRate = 25 and beyond but require careful data sheet analysis.
SPI Flash PROM Density Requirements
Table 49 shows the smallest usable SPI Flash PROM to program a single Spartan-3E FPGA. Commercially available SPI Flash PROMs range in density from 1 Mbit to 128 Mbits. A multiple-FPGA daisy-chained application requires a SPI Flash PROM large enough to contain the sum of the FPGA file sizes. An application can also use a larger-density SPI Flash PROM to hold additional data beyond just FPGA configuration data. For example, the SPI Flash PROM can also store application code for a MicroBlazeTM RISC processor core integrated in the Spartan-3E FPGA. See Using the SPI Flash Interface after Configuration.
Using the SPI Flash Interface after Configuration
After the FPGA successfully completes configuration, all of the pins connected to the SPI Flash PROM are available as user-I/O pins. If not using the SPI Flash PROM after configuration, drive CSO_B High to disable the PROM. The MOSI, DIN, and CCLK pins are then available to the FPGA application. Because all the interface pins are user I/O after configuration, the FPGA application can continue to use the SPI Flash interface pins to communicate with the SPI Flash PROM, as shown in Figure 53. SPI Flash PROMs offer random-accessible, byte-addressable, read/write, non-volatile storage to the FPGA application. SPI Flash PROMs are available in densities ranging from 1 Mbit up to 128 Mbits. However, a single Spartan-3E FPGA requires less than 6 Mbits. If desired, use a larger SPI Flash PROM to contain additional non-volatile application data, such as MicroBlaze processor code, or other user data such as serial numbers and Ethernet MAC IDs. In the example shown in Figure 53, the FPGA configures from SPI Flash PROM. Then using FPGA logic after configuration, the FPGA copies MicroBlaze code from SPI Flash into external DDR SDRAM for code execution. Similarly, the FPGA application can store non-volatile application data within the SPI Flash PROM. The FPGA configuration data is stored starting at location 0. Store any additional data beginning in the next available SPI Flash PROM sector or page. Do not mix configuration data and user data in the same sector or page.
Table 49: Number of Bits to Program a Spartan-3E FPGA and Smallest SPI Flash PROM
Number of Configuration Bits 581,344 1,352,192 2,267,136 3,832,320 5,957,760 Smallest Usable SPI Flash PROM 1 Mbit 2 Mbit 4 Mbit 4 Mbit 8 Mbit
Device XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E
CCLK Frequency
In SPI Flash mode, the FPGA's internal oscillator generates the configuration clock frequency. The FPGA provides this clock on its CCLK output pin, driving the PROM's clock input pin. The FPGA starts configuration at its lowest frequency and increases its frequency for the remainder of the configuration process if so specified in the configuration bitstream. The maximum frequency is specified using the ConfigRate bitstream generator option. The maximum frequency supported by the FPGA configuration logic depends on the tim-
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Spartan-3E FPGA
SPI Serial Flash PROM
DDR SDRAM
MOSI DIN FPGA-based SPI Master CCLK CSO_B User-I/O +3.3V
DATA_IN DATA_OUT CLOCK SELECT
User Data MicroBlaze Code FPGA Configuration
FFFFF
0
4.7k
SPI Peripherals
DATA_IN DATA_OUT CLOCK SELECT
* A/D Converter * D/A Converter * CAN Controller * Temperature Sensor * Displays * Temperature Sensor * Microcontroller * ASSP
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To other SPI slave peripherals
Figure 53: Using the SPI Flash Interface After Configuration
Similarly, the SPI bus can be expanded to additional SPI peripherals. Because SPI is a common industry-standard interface, there are a variety of SPI-based peripherals available, including analog-to-digital (A/D) converters, digital-to-analog (D/A) converters, CAN controllers, and temperature sensors. The MOSI, DIN, and CCLK pins are common to all SPI peripherals. Connect the select input on each additional SPI peripheral to one of the FPGA user I/O pins. If HSWAP = 0 during configuration, the FPGA holds the select line High. If HSWAP = 1, connect the select line to +3.3V via an external 4.7 k pull-up resistor to avoid spurious read or write operations. After configuration, drive the select line Low to select the desired SPI peripheral. Refer to the individual SPI peripheral data sheet for specific interface and communication protocol requirements.
Daisy-Chaining
If the application requires multiple FPGAs with different configurations, then configure the FPGAs using a daisy chain, as shown in Figure 54. Use SPI Flash mode (M[2:0] = <0:0:1>) for the FPGA connected to the Platform Flash PROM and Slave Serial mode (M[2:0] = <1:1:1>) for all other FPGAs in the daisy-chain. After the master FPGA--the FPGA on the left in the diagram--finishes loading its configuration data from the SPI Flash PROM, the master device uses its DOUT output pin to supply data to the next device in the daisy-chain, on the falling CCLK edge.
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Functional Description
CCLK +1.2V +3.3V +1.2V
P
4.7k
VCCINT HSWAP VCCO_0 VCCO_2 MOSI DIN CSO_B
VCCO_0 +3.3V
P
SPI Serial Flash
VCC DATA_IN DATA_OUT SELECT WR_PROTECT HOLD CLOCK GND
I
P
Slave Serial Mode `1' `1' `1'
HSWAP
VCCINT VCCO_0 VCCO_2
VCCO_0 +3.3V
SPI Mode `0' `0' `1' Variant Select `1' M2 M1 M0
W
`1'
M2 M1 M0
S
`1'
VS2 VS1 VS0
Spartan-3E FPGA
CCLK DOUT INIT_B VCCAUX TDO +2.5V
Spartan-3E FPGA
CCLK DIN
DOUT INIT_B VCCAUX TDO +2.5V
DOUT
+2.5V JTAG TDI TMS TCK TDO
TDI TMS TCK PROG_B GND
+2.5V DONE
+3.3V
TDI TMS TCK PROG_B
DONE GND
4.7k
4.7k
330
PROG_B Recommend open-drain driver
PROG_B TCK TMS DONE INIT_B
DS312-2_48_021405
Figure 54: Daisy-Chaining from SPI Flash Mode
In-System Programming Support
I In a production application, the SPI Flash PROM is usually pre-programmed before it is mounted on the printed circuit board. In-system programming support is available from some third-party PROM programmers using a socket adapter with attached wires. To gain access to the SPI Flash signals, drive the FPGA's PROG_B input Low with an open-drain driver. This action places all FPGA I/O pins, including those attached to the SPI Flash, in high-impedance (Hi-Z). If the HSWAP input is High, the I/Os have pull-up resistors to the VCCO input on their respective I/O bank. The external programming hardware then has direct access to the SPI Flash pins. The programming access points are highlighted in the gray box in Figure 50, Figure 51, and Figure 54.
to a 24-bit address lines to access an attached parallel Flash. Only 20 address lines are generated for Spartan-3E FPGAs in the TQ144 package. The BPI mode is not available for Spartan-3E FPGAs in the VQ100 package. The interface is designed for standard parallel NOR Flash PROMs and supports both byte-wide (x8) and byte-wide/halfword (x8/x16) PROMs. The interface does not support halfword-only (x16) PROMs. The interface works equally wells with other memories that use a similar interface such as SRAM, NVRAM, EEPROM, EPROM, or masked ROM but is primarily designed for Flash memory. There is another type of Flash memory called NAND Flash, which is commonly used in memory cards for digital cameras, etc. Spartan-3E FPGAs do not configure directly from NAND Flash memories. The FPGA's internal oscillator controls the interface timing and the FPGA supplies the clock on the CCLK output pin. However, the CCLK signal is not used in single FPGA applications. Similarly, the FPGA drives three pins Low during configuration (LDC[2:0]) and one pin High during configuration (HDC) to the PROM's control inputs.
Byte-Wide Peripheral Interface (BPI) Parallel Flash Mode
In Byte-wide Peripheral Interface (BPI) mode (M[2:0] = <0:1:0> or <0:1:1>), a Spartan-3E FPGA configures itself from an industry-standard parallel NOR Flash PROM, as illustrated in Figure 55. The FPGA generates up
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+1.2V
P
VCCINT HSWAP VCCO_0 VCCO_1 LDC0 LDC1 HDC LDC2 A[16:0] VCCO_2 D[7:0] A[23:17]
V
VCCO_0
V
I
VCCO
Not available in VQ100 package
BPI Mode `0' `1' M2 M1 M0
x8 or CE# OE# x8/x16 Flash WE# PROM BYTE# D
DQ[15:7]
V
DQ[7:0] A[n:0] GND
A
V
4.7k
Spartan-3E BUSY FPGA CCLK
+2.5V JTAG TDI TMS TCK TDO `0' `0' CSI_B RDWR_B TDI TMS TCK PROG_B GND CSO_B INIT_B VCCAUX TDO
+2.5V
+2.5V
DONE
PROG_B Recommend open-drain driver
DS312-2_49_022305
Figure 55: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs
A During configuration, the value of the M0 mode pin
determines how the FPGA generates addresses, as shown Table 50. When M0 = 0, the FPGA generates addresses starting at 0 and increments the address on every falling CCLK edge. Conversely, when M0 = 1, the FPGA generates addresses starting at 0xFF_FFFF (all ones) and decrements the address on every falling CCLK edge.
Depending on the specific processor architecture, the processor boots either from the top or bottom of memory. The FPGA is flexible and boots from the opposite end of memory from the processor. Only the processor or the FPGA can boot at any given time. The FPGA can configure first, holding the processor in reset or the processor can boot first, asserting the FPGA's PROG_B pin. The mode select pins, M[2:0], are sampled when the FPGA's INIT_B output goes High and must be at defined logic levels during this time. After configuration, when the FPGA's DONE output goes High, the mode pins are available as full-featured user-I/O pins.
P Similarly, the FPGA's HSWAP pin must be Low to enable pull-up resistors on all user-I/O pins or High to disable the pull-up resistors. The HSWAP control must remain at a constant logic level throughout FPGA configuration. After configuration, when the FPGA's DONE output goes
Table 50: BPI Addressing Control
M2 0 M1 1 1 0xFF_FFFF Decrementing M0 0 Start Address 0 Addressing Incrementing
This addressing flexibility allows the FPGA to share the parallel Flash PROM with an external or embedded processor.
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Functional Description actively drives during configuration and is available as a user I/O after configuration. After configuration, all of the interface pins except DONE and PROG_B are available as user I/Os. Furthermore, the bidirectional SelectMAP configuration peripheral interface (see Slave Parallel Mode) is available after configuration. To continue using SelectMAP mode, set the Persist bitstream generator option to Yes. An external host can then read and verify configuration data.
High, the HSWAP pin is available as full-featured user-I/O pin and is powered by the VCCO_0 supply. The RDWR_B and CSI_B must be Low throughout the configuration process. After configuration, these pins also become user I/O. In a single-FPGA application, the FPGA's CSO_B and CCLK pins are not used but are actively driving during the configuration process. The BUSY pin is not used but also
Table 51: Byte-Wide Peripheral Interface (BPI) Connections
Pin Name HSWAP FPGA Direction Input Description User I/O Pull-Up Control. When Low during configuration, enables pull-up resistors in all I/O pins to respective I/O bank VCCO input. 0: Pull-ups during configuration 1: No pull-ups M[2:0] Input Mode Select. Selects the FPGA configuration mode. M2 = 0, M1 = 1. Set M0 = 0 to start at address 0, increment addresses. Set M0 = 1 to start at address 0xFFFFFF and decrement addresses. Sampled when INIT_B goes High. Must be Low throughout configuration. User I/O During Configuration Drive at valid logic level throughout configuration. After Configuration User I/O
P
A
CSI_B
Input
Chip Select Input. Active Low.
User I/O. If bitstream option Persist=Yes, becomes part of SelectMap parallel peripheral interface. User I/O. If bitstream option Persist=Yes, becomes part of SelectMap parallel peripheral interface. User I/O
RDWR_B
Input
Read/Write Control. Active Low write enable. Read functionality typically only used after configuration, if bitstream option Persist=Yes. PROM Chip Enable
Must be Low throughout configuration.
LDC0
Output
Connect to PROM chip-select input (CE#). FPGA drives this signal Low throughout configuration. Connect to PROM output-enable input (OE#). FPGA drives this signal Low throughout configuration. Connect to PROM write-enable input (WE#). FPGA drives this signal High throughout configuration. This signal is not used for x8 PROMs. For PROMs with a x8/x16 data width control, connect to PROM byte-mode input (BYTE#). See Precautions Using x8/x16 Flash PROMs. FPGA drives this signal Low throughout configuration.
LDC1
Output
PROM Output Enable
User I/O
HDC
Output
PROM Write Enable
User I/O
LDC2 D
Output
PROM Byte Mode
User I/O. Drive this pin High after configuration to use a x8/x16 PROM in x16 mode.
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Table 51: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
Pin Name A[23:0] FPGA Direction Output Address Description During Configuration Connect to PROM address inputs. High order address lines may not be available in all packages and not all may be required. Number of address lines required depends on the size of the attached Flash PROM. FPGA address generation controlled by M0 mode pin. Addresses presented on falling CCLK edge. Only 20 address lines are available in TQ144 package. D[7:0] Input Data Input FPGA receives byte-wide data on these pins in response the address presented on A[23:0]. Data captured by FPGA Not used in single FPGA applications. In a daisy-chain configuration, this pin connects to the CSI_B pin of the next FPGA in the chain. Actively drives. Not used during configuration but actively drives. User I/O If bitstream option Persist=Yes, becomes part of SelectMap parallel peripheral interface. User I/O After Configuration User I/O
CSO_B
Output
Chip Select Output. Active Low.
BUSY
Output
Busy Indicator. Typically only used after configuration, if bitstream option Persist=Yes.
User I/O. If bitstream option Persist=Yes, becomes part of SelectMap parallel peripheral interface. User I/O If bitstream option Persist=Yes, becomes part of SelectMap parallel peripheral interface.
CCLK
Output
Configuration Clock. Generated by FPGA internal oscillator. Frequency controlled by ConfigRate bitstream generator option. If CCLK PCB trace is long or has multiple connections, terminate this output to maintain signal integrity. Initialization Indicator. Active Low. Goes Low at start of configuration during Initialization memory clearing process. Released at end of memory clearing, when mode select pins are sampled. In daisy-chain applications, this signal requires an external 4.7 k pull-up resistor to VCCO_2.
Not used in single FPGA applications but actively drives. In a daisy-chain configuration, drives the CCLK inputs of all other FPGAs in the daisy-chain.
INIT_B
Open-drain bidirectional I/O
Active during configuration. If CRC error detected during configuration, FPGA drives INIT_B Low.
User I/O
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Table 51: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
Pin Name DONE FPGA Direction Open-drain bidirectional I/O Description FPGA Configuration Done. Low during configuration. Goes High when FPGA successfully completes configuration. Requires external 330 pull-up resistor to 2.5V. Program FPGA. Active Low. When asserted Low for 300 ns or longer, forces the FPGA to restart its configuration process by clearing configuration memory and resetting the DONE and INIT_B pins once PROG_B returns High. Requires external 4.7 k pull-up resistor to 2.5V. If driving externally, use an open-drain or open-collector driver. During Configuration Low indicates that the FPGA is not yet configured. After Configuration Pulled High via external pull-up. When High, indicates that the FPGA successfully configured.
PROG_B
Input
Must be High to allow configuration to start.
Drive PROG_B Low and release to reprogram FPGA. Hold PROG_B to force FPGA I/O pins into Hi-Z, allowing direct programming access to Flash PROM pins.
Voltage Compatibility
V The FPGA's parallel Flash interface signals are within I/O Banks 1 and 2. The majority of parallel Flash PROMs use a single 3.3V supply voltage. Consequently, in most cases, the FPGA's VCCO_1 and VCCO_2 supply voltages must also be 3.3V to match the parallel Flash PROM. There are some 1.8V parallel Flash PROMs available and the FPGA interfaces with these devices if the VCCO_1 and VCCO_2 supplies are also 1.8V.
shows the minimum required number of address lines between the FPGA and parallel Flash PROM. The actual number of address line required depends on the density of the attached parallel Flash PROM. A multiple-FPGA daisy-chained application requires a parallel Flash PROM large enough to contain the sum of the FPGA file sizes. An application may also use a larger-density parallel Flash PROM to hold additional data beyond just FPGA configuration data. For example, the parallel Flash PROM could also contain the application code for a MicroBlaze RISC processor core implemented within the Spartan-3E FPGA. After configuration, the MicroBlaze processor could execute directly from external Flash or could copy the code to other, faster system memory before executing the code.
Supported Parallel NOR Flash PROM Densities
Table 52 indicates the smallest usable parallel Flash PROM to program a single Spartan-3E FPGA. Parallel Flash density is specified in bits but addressed as bytes. The FPGA presents up to 24 address lines during configuration but not all are required for single FPGA applications. Table 52
Table 52: Number of Bits to Program a Spartan-3E FPGA and Smallest Parallel Flash PROM
Device XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E Uncompressed File Sizes (bits) 581,344 1,352,192 2,267,136 3,832,320 5,957,760 Smallest Usable Parallel Flash PROM 1 Mbit 2 Mbit 4 Mbit 4 Mbit 8 Mbit Minimum Required Address Lines A[16:0] A[17:0] A[18:0] A[18:0] A[19:0]
CCLK Frequency
In BPI mode, the FPGA's internal oscillator generates the configuration clock frequency that controls all the interface timing. The FPGA starts configuration at its lowest frequency and increases its frequency for the remainder of the configuration process if so specified in the configuration bit-
stream. The maximum frequency is specified using the ConfigRate bitstream generator option. Table 53 shows the maximum ConfigRate settings, approximately equal to MHz, for various PROM read access times. Despite using slower ConfigRate settings, BPI mode is equally fast as the other configuration modes. In BPI mode, data is accessed
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Table 53: Maximum ConfigRate Settings for Parallel Flash PROMs
Flash Read Access Time < 200 ns < 90 ns Maximum ConfigRate Setting 3 6
ous read or write operations. After configuration, drive the select line Low to select the desired peripheral. Refer to the individual peripheral data sheet for specific interface and communication protocol requirements. The FPGA optionally supports a 16-bit peripheral interface by driving the LDC2 (BYTE#) control pin High after configuration. See Precautions Using x8/x16 Flash PROMs for additional information. The FPGA provides up to 24 address lines during configuration, addressing up to 128 Mbits (16 Mbytes). If using a larger parallel PROM, connect the upper address lines to FPGA user I/O. During configuration, the upper address lines will be pulled High if HSWAP = 0. Otherwise, use external pull-up or pull-down resistors on these address lines to define their values during configuration.
Using the BPI Interface after Configuration
After the FPGA successfully completes configuration, all of the pins connected to the parallel Flash PROM are available as user I/Os. If not using the parallel Flash PROM after configuration, drive LDC0 High to disable the PROM's chip-select input. The remainder of the BPI pins then become available to the FPGA application, including all 24 address lines, the eight data lines, and the LDC2, LDC1, and HDC control pins. Because all the interface pins are user I/Os after configuration, the FPGA application can continue to use the interface pins to communicate with the parallel Flash PROM. Parallel Flash PROMs are available in densities ranging from 1 Mbit up to 128 Mbits and beyond. However, a single Spartan-3E FPGA requires less than 6 Mbits for configuration. If desired, use a larger parallel Flash PROM to contain additional non-volatile application data, such as MicroBlaze processor code, or other user data such as serial numbers, Ethernet MAC IDs, etc. In such an example, the FPGA configures from parallel Flash PROM. Then using FPGA logic after configuration, a MicroBlaze processor embedded within the FPGA can either execute code directly from parallel Flash PROM or copy the code to external DDR SDRAM and execute from DDR SDRAM. Similarly, the FPGA application can store non-volatile application data within the parallel Flash PROM. The FPGA configuration data is stored starting at either at location 0 or the top of memory (addresses all ones) or at both locations for MultiBoot mode. Store any additional data beginning in other available parallel Flash PROM sectors. Do not mix configuration data and user data in the same sector. Similarly, the parallel Flash PROM interface can be expanded to additional parallel peripherals. The address, data, and LDC1 (OE#) and HDC (WE#) control signals are common to all parallel peripherals. Connect the chip-select input on each additional peripheral to one of the FPGA user I/O pins. If HSWAP = 0 during configuration, the FPGA holds the chip-select line High via an internal pull-up resistor. If HSWAP = 1, connect the select line to +3.3V via an external 4.7 k pull-up resistor to avoid spuri-
Precautions Using x8/x16 Flash PROMs
D Most low- to mid-density PROMs are byte-wide (x8)
only. Many higher-density Flash PROMs support both byte-wide (x8) and halfword-wide (x16) data paths and include a mode input called BYTE# that switches between x8 or x16. During configuration, Spartan-3E FPGAs only support byte-wide data. However, after configuration, the FPGA supports either x8 or x16 modes. In x16 mode, up to eight additional user I/O pins are required for the upper data bits, D[15:8]. Connecting a Spartan-3E FPGA to a x8/x16 Flash PROM is simple, but does require a precaution. Various Flash PROM vendors use slightly different interfaces to support both x8 and x16 modes. Some vendors (Intel, Micron, some STMicroelectronics devices) use a straightforward interface with pin naming that matches the FPGA connections. However, the PROM's A0 pin is wasted in x16 applications and a separate FPGA user-I/O pin is required for the D15 data line. Fortunately, the FPGA A0 pin is still available as a user I/O after configuration, even though it connects to the Flash PROM. Other vendors (AMD, Atmel, Silicon Storage Technology, some STMicroelectronics devices) use a pin-efficient interface but change the function of one pin, called IO15/A-1, depending if the PROM is in x8 or x16 mode. In x8 mode, BYTE# = 0, this pin is the least-significant address line. The A0 address line selects the halfword location. The A-1 address line selects the byte location. When in x16 mode, BYTE# = 1, the IO15/A-1 pin becomes the most-significant data bit, D15 because byte addressing is not required in this mode. Check to see if the Flash PROM has a pin named "IO15/A-1" or "DQ15/A-1". If so, be careful to connect x8/x16 Flash PROMs correctly, as shown in Table 54. Also, remember that the D[14:8] data connections require FPGA user I/O pins but that the D15 data is already connected for the FPGA's A0 pin.
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Functional Description
Table 54: FPGA Connections to Flash PROM with "IO15/A-1" Pin
FPGA Pin LDC2 Connection to Flash PROM with IO15/A-1 Pin BYTE# x8 Flash PROM Interface After FPGA Configuration Drive LDC2 Low or leave unconnected and tie PROM BYTE# input to GND Active-Low Flash PROM output-enable control Active-Low Flash PROM chip-select control Flash PROM write-enable control A[n:0] IO15/A-1 is least-significant address input IO[7:0] Upper data lines IO[14:8] not required x16 Flash PROM Interface After FPGA Configuration Drive LCD2 High
LDC1 LDC0 HDC A[23:1] A0 D[7:0] User I/O
OE# CS# WE# A[n:0] IO15/A-1 IO[7:0] Upper data lines IO[14:8] not required unless used as x16 Flash interface after configuration
Active-Low Flash PROM output-enable control Active-Low Flash PROM chip-select control Flash PROM write-enable control A[n:0] IO15/A-1 is most-significant data line, IO15 IO[7:0] IO[14:8]
Daisy-Chaining
If the application requires multiple FPGAs with different configurations, then configure the FPGAs using a daisy chain, as shown in Figure 56. Use BPI mode (M[2:0] = <0:1:0> or <0:1:1>) for the FPGA connected to the parallel NOR Flash PROM and Slave Parallel mode (M[2:0] = <1:1:0>) for all other FPGAs in the daisy-chain. After the master FPGA--the FPGA on the left in the diagram--finishes loading its configuration data from the parallel Flash PROM, the master device continues generating addresses to the Flash PROM and asserts its CSO_B output Low, enabling the
next FPGA in the daisy-chain. The next FPGA then receives parallel configuration data from the Flash PROM. The master FPGA's CCLK output synchronizes data capture. The downstream devices in Slave Parallel mode also actively drive their LDC[2:0] and HDC outputs during configuration, although these signal are not used for configuration. These pins are in I/O Bank 1, powered by VCCO_1. Because these pins do not connect elsewhere in the configuration circuit, the voltage on VCCO_1 can be whatever is required by the end application.
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Functional Description
R
CCLK D[7:0] +1.2V +1.2V
P
VCCINT HSWAP VCCO_0 VCCO_1 LDC0 LDC1 HDC LDC2 A[16:0] VCCO_2 D[7:0] A[23:17]
V
VCCO_0
V
I
P
VCC
HSWAP
VCCINT VCCO_0 VCCO_1 LDC0 LDC1 HDC LDC2
VCCO_0 VCCO_1
Not available in VQ100 package
BPI Mode `0' `1' M2 M1 M0
x8 or CE# OE# x8/x16 Flash WE# PROM BYTE# D
DQ[15:7] Slave Parallel Mode `1' `1' `0' M2 M1 M0 CCLK FPGA CSI_B RDWR_B TDI TMS TCK PROG_B
V
DQ[7:0] A[n:0] GND
VCCO_2 D[7:0]
V
A
Spartan-3E BUSY FPGA CCLK
2.5V JTAG TDI TMS TCK TDO `0' `0' CSI_B RDWR_B TDI TMS TCK PROG_B GND CSO_B INIT_B VCCAUX TDO +2.5V `0'
Spartan-3E BUSY
CSO_B INIT_B VCCAUX TDO +2.5V CSO_B
+2.5V DONE
V
DONE GND
4.7k
4.7k
330
PROG_B Recommend open-drain driver
PROG_B TCK TMS DONE INIT_B
DS312-2_50_021405
Figure 56: Daisy-Chaining from BPI Flash Mode
In-System Programming Support
In a production application, the parallel Flash PROM is usually preprogrammed before it is mounted on the printed circuit board. In-system programming support is available from third-party boundary-scan tool vendors and from some third-party PROM programmers using a socket adapter with attached wires. To gain access to the parallel Flash signals, drive the FPGA's PROG_B input Low with an open-drain driver. This action places all FPGA I/O pins, including those attached to the parallel Flash, in high-impedance (Hi-Z). If the HSWAP input is High, the I/Os have pull-up resistors to the VCCO input on their respective I/O bank. The external programming hardware then has direct access to the parallel Flash pins. The programming access points are highlighted in the gray boxes in Figure 55 and Figure 56. The FPGA itself can also be used as a parallel Flash PROM programmer during development and test phases. Initially, an FPGA-based programmer is downloaded into the FPGA via JTAG. Then the FPGA performs the Flash PROM programming algorithms and receives programming data from the host via the FPGA's JTAG interface. See Chapter 11 in "Embedded System Tools Reference Manual".
I
Dynamically Loading Multiple Configuration Images Using MultiBoot Option
After the FPGA configures itself using BPI mode from one end of the parallel Flash PROM, then the FPGA can trigger a MultiBoot event and reconfigure itself from the opposite end of the parallel Flash PROM. MultiBoot is only available when using BPI mode and only for applications with a single Spartan-3E FPGA. By default, MultiBoot mode is disabled. To trigger a MultiBoot event, assert a Low pulse lasting at least 300 ns on the MultiBoot Trigger (MBT) input to the STARTUP_SPARTAN3E library primitive. Figure 57 shows an example usage. At power up, the FPGA loads itself from the attached parallel Flash PROM. In this example, the M0 mode pin is Low so the FPGA starts at address 0 and increments through the Flash PROM memory locations. After the FPGA completes configuration, the application loaded into the FPGA performs a board-level or system test using FPGA logic. If the test is successful, the FPGA triggers a MultiBoot event, causing the FPGA to reconfigure from the opposite end of the Flash PROM memory. This second configuration contains the FPGA application for normal operation.
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Parallel Flash PROM
FFFFFF
Parallel Flash PROM
FFFFFF
General FPGA Application
STARTUP_SPARTAN3E GSR
General FPGA Application
User Area
> 300 ns
GTS MBT CLK
User Area
Diagnostics FPGA Application 0 First Configuration
Reconfigure
Diagnostics FPGA Application 0 Second Configuration
DS312-2_51_021405
Figure 57: Use MultiBoot to Load Alternate Configuration Images
Similarly, the general FPGA application could trigger a MultiBoot event at any time to reload the diagnostics design. In another potential application, the initial design loaded into the FPGA image contains a "golden" or "fail-safe" configuration image, which then communicates with the outside world and checks for a newer image. If there is a new configuration revision and the new image verifies as good, the "golden" configuration triggers a MultiBoot event to load the new image. When a MultiBoot event is triggered, the FPGA then again drives its configuration pins as described in Table 51. However, the FPGA does not assert the PROG_B pin. The system design must ensure that no other device drives on these same pins during the reconfiguration process. The FPGA's DONE, LDC[2:0], or HDC pins can temporarily disable any conflicting drivers during reconfiguration.
Slave Parallel Mode
In Slave Parallel mode (M[2:0] = <1:1:0>), an external host such as a microprocessor or microcontroller writes byte-wide configuration data into the FPGA, using a typical peripheral interface as shown in Figure 58.
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Functional Description
R
+1.2V
P
HSWAP
VCCINT VCCO_0 VCCO_1 LDC0 LDC1 HDC LDC2 VCCO_2
VCCO_0 VCCO_1
Slave Parallel Mode
V Intelligent Download Host
Configuration Memory Source * Internal memory * Disk drive * Over network * Over RF link VCC D[7:0] BUSY SELECT READ/WRITE CLOCK PROG_B DONE INIT_B GND * Microcontroller * Processor * Tester * Computer
V V
4.7k
+2.5V +2.5V
`1' `1' `0'
M2 M1 M0 D[7:0] FPGA BUSY CSI_B CSO_B INIT_B RDWR_B CCLK VCCAUX TDO
Spartan-3E
TDI TMS TCK PROG_B GND
DONE
PROG_B Recommend open-drain +2.5V driver JTAG TDI TMS TCK TDO
DS312-2_52_022205
Figure 58: Slave Parallel Configuration Mode
The external download host starts the configuration process by pulsing PROG_B and monitoring that the INIT_B pin goes High, indicating that the FPGA is ready to receive its first data. The host asserts the active-Low chip-select signal (CSI_B) and the active-Low Write signal (RDWR_B). The host then continues supplying data and clock signals until either the FPGA's DONE pin goes High, indicating a successful configuration, or until the FPGA's INIT_B pin goes Low, indicating a configuration error. The FPGA captures data on the rising CCLK edge. If the CCLK frequency exceeds 50 MHz, then the host must also monitor the FPGA's BUSY output. If the FPGA asserts BUSY High, the host must hold the data for an additional clock cycle, until BUSY returns Low. If the CCLK frequency
80
is 50 MHz or below, the BUSY pin may be ignored but actively drives during configuration. The configuration process requires more clock cycles than indicated from the configuration file size. Additional clocks are required during the FPGA's start-up sequence, especially if the FPGA is programmed to wait for selected Digital Clock Managers (DCMs) to lock to their respective clock inputs (see Start-Up, page 91). If the Slave Parallel interface is only used to configure the FPGA, never to read data back, then the RDWR_B signal can also be eliminated from the interface. However, RDWR_B must remain Low during configuration.
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Functional Description The Slave Parallel mode is also used with BPI mode to create multi-FPGA daisy-chains. The lead FPGA is set for BPI mode configuration; all the downstream daisy-chain FPGAs are set for Slave Parallel configuration, as highlighted in Figure 56.
After configuration, all of the interface pins except DONE and PROG_B are available as user I/Os. Alternatively, the bidirectional SelectMAP configuration interface is available after configuration. To continue using SelectMAP mode, set the Persist bitstream generator option to Yes. The external host can then read and verify configuration data.
Table 55: Slave Parallel Mode Connections
Pin Name HSWAP FPGA Direction Input Description User I/O Pull-Up Control. When Low during configuration, enables pull-up resistors in all I/O pins to respective I/O bank VCCO input. 0: Pull-ups during configuration 1: No pull-ups M[2:0] D[7:0] Input Input Mode Select. Selects the FPGA configuration mode. Data Input. M2 = 1, M1 = 1, M0 = 0 Sampled when INIT_B goes High. Byte-wide data provided by host. FPGA captures data on rising CCLK edge. User I/O User I/O. If bitstream option Persist=Yes, becomes part of SelectMap parallel peripheral interface. User I/O. If bitstream option Persist=Yes, becomes part of SelectMap parallel peripheral interface. During Configuration Drive at valid logic level throughout configuration. After Configuration User I/O
BUSY
Output
Busy Indicator.
If CCLK frequency is < 50 MHz, this pin may be ignored. When High, indicates that the FPGA is not ready to receive additional configuration data. Host must hold data an additional clock cycle. Must be Low throughout configuration.
CSI_B
Input
Chip Select Input. Active Low.
User I/O. If bitstream option Persist=Yes, becomes part of SelectMap parallel peripheral interface. User I/O. If bitstream option Persist=Yes, becomes part of SelectMap parallel peripheral interface. User I/O If bitstream option Persist=Yes, becomes part of SelectMap parallel peripheral interface. User I/O
RDWR_B
Input
Read/Write Control. Active Low write enable.
Must be Low throughout configuration.
CCLK
Input
Configuration Clock. If CCLK PCB trace is long or has multiple connections, terminate this output to maintain signal integrity. Low During Configuration.
External clock.
LDC[2:0]
Output
These pins are not used during configuration. Low throughout configuration. This pin is not used during configuration. High throughout configuration.
HDC
Output
High During Configuration.
User I/O
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Functional Description
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Table 55: Slave Parallel Mode Connections (Continued)
Pin Name CSO_B FPGA Direction Output Description Chip Select Output. Active Low. During Configuration Not used in single FPGA applications. In a daisy-chain configuration, this pin connects to the CSI_B pin of the next FPGA in the chain. Actively drives. Active during configuration. If CRC error detected during configuration, FPGA drives INIT_B Low. After Configuration User I/O
INIT_B
Open-drain bidirectional I/O
Initialization Indicator. Active Low. Goes Low at start of configuration during Initialization memory clearing process. Released at end of memory clearing, when mode select pins are sampled. In daisy-chain applications, this signal requires an external 4.7 k pull-up resistor to VCCO_2. FPGA Configuration Done. Low during configuration. Goes High when FPGA successfully completes configuration. Requires external 330 pull-up resistor to 2.5V. Program FPGA. Active Low. When asserted Low for 300 ns or longer, forces the FPGA to restart its configuration process by clearing configuration memory and resetting the DONE and INIT_B pins once PROG_B returns High. Requires external 4.7 k pull-up resistor to 2.5V. If driving externally, use an open-drain or open-collector driver.
User I/O
DONE
Open-drain bidirectional I/O
Low indicates that the FPGA is not yet configured.
Pulled High via external pull-up. When High, indicates that the FPGA successfully configured.
PROG_B
Input
Must be High to allow configuration to start.
Drive PROG_B Low and release to reprogram FPGA.
Voltage Compatibility
V Most Slave Parallel interface signals are within the FPGA's I/O Bank 2, supplied by the VCCO_2 supply input. The VCCO_2 voltage can be 1.8V, 2.5V, or 3.3V to match the requirements of the external host, ideally 2.5V. Using 1.8V or 3.3V requires additional design considerations as the DONE and PROG_B pins are powered by the FPGA's 2.5V VCCAUX supply. See application note XAPP453: "The 3.3V Configuration of Spartan-3 FPGAs" for additional information.
Daisy-Chaining
If the application requires multiple FPGAs with different configurations, then configure the FPGAs using a daisy chain. Use Slave Parallel mode (M[2:0] = <1:1:0>) for all FPGAs in the daisy-chain. The schematic in Figure 59 is optimized for FPGA downloading and does not support the SelectMAP read interface. The FPGA's RDWR_B pin must be Low during configuration. After the lead FPGA is filled with its configuration data, the lead FPGA enables the next FPGA in the daisy-chain by asserting is chip-select output, CSO_B.
The LDC[2:0] and HDC signal are active in I/O Bank 1 but are not used in the interface. Consequently, VCCO_1 can be set the appropriate voltage for the application.
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D[7:0] CCLK +1.2V +1.2V
P
HSWAP
VCCINT VCCO_0 VCCO_1 LDC0 LDC1 HDC LDC2 VCCO_2
VCCO_0 VCCO_1
P
HSWAP
VCCINT VCCO_0 VCCO_1 LDC0 LDC1 HDC LDC2 VCCO_2
VCCO_0 VCCO_1
Slave Parallel Mode
V Intelligent Download Host
Configuration Memory Source VCC DATA[7:0] BUSY SELECT READ/WRITE CLOCK PROG_B DONE INIT_B GND
V V
4.7k
Slave Parallel Mode `1' `1' `0' M2 M1 M0
V
`1' `1' `0'
M2 M1 M0
* Internal memory * Disk drive * Over network * Over RF link
`0'
BUSY CSI_B RDWR_B CCLK
Spartan-3E D[7:0] FPGA
CSO_B INIT_B
`0'
D[7:0] FPGA BUSY CSI_B CSO_B RDWR_B INIT_B CCLK VCCAUX TDO +2.5V
Spartan-3E
CSO_B
TDI TMS TCK PROG_B GND
VCCAUX TDO
+2.5V TDI TMS TCK PROG_B
+2.5V DONE
4.7k
330
*Microcontroller *Processor *Tester
PROG_B Recommend open-drain 2.5V driver JTAG TDI TMS TCK TDO
DONE GND
PROG_B DONE INIT_B TMS TCK
DS312-2_53_022305
Figure 59: Daisy-Chaining using Slave Parallel Mode
Slave Serial Mode
In Slave Serial mode (M[2:0] = <1:1:1>), an external host such as a microprocessor or microcontroller writes serial configuration data into the FPGA, using the synchronous serial interface shown in Figure 60. The serial configuration data is presented on the FPGA's DIN input pin with sufficient setup time before each rising edge of the externally generated CCLK clock input. The intelligent host starts the configuration process by pulsing PROG_B and monitoring that the INIT_B pin goes High,
indicating that the FPGA is ready to receive its first data. The host then continues supplying data and clock signals until either the DONE pin goes High, indicating a successful configuration, or until the INIT_B pin goes Low, indicating a configuration error. The configuration process requires more clock cycles than indicated from the configuration file size. Additional clocks are required during the FPGA's start-up sequence, especially if the FPGA is programmed to wait for selected Digital Clock Managers (DCMs) to lock to their respective clock inputs (see Start-Up, page 91).
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Functional Description
R
+1.2V
P
Slave Serial Mode
HSWAP
VCCINT VCCO_0 VCCO_2
VCCO_0
V V
Configuration Memory Source * Internal memory * Disk drive * Over network * Over RF link
VCC CLOCK SERIAL_OUT PROG_B DONE INIT_B GND * Microcontroller * Processor * Tester * Computer
CCLK DIN
Spartan-3E FPGA
DOUT INIT_B VCCAUX TDO +2.5V
TDI TMS TCK PROG_B GND
4.7k
Intelligent V Download Host
`1' `1' `1'
M2 M1 M0
+2.5V DONE
PROG_B Recommend open-drain driver +2.5V JTAG TDI TMS TCK TDO
DS312-2_54_022305
Figure 60: Slave Serial Configuration
The mode select pins, M[2:0], are sampled when the FPGA's INIT_B output goes High and must be at defined logic levels during this time. After configuration, when the FPGA's DONE output goes High, the mode pins are available as full-featured user-I/O pins.
P Similarly, the FPGA's HSWAP pin must be Low to enable pull-up resistors on all user-I/O pins or High to disable the pull-up resistors. The HSWAP control must remain at a constant logic level throughout FPGA configuration. After configuration, when the FPGA's DONE output goes High, the HSWAP pin is available as full-featured user-I/O pin and is powered by the VCCO_0 supply.
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Table 56: Slave Serial Mode Connections
Pin Name HSWAP FPGA Direction Input Description User I/O Pull-Up Control. When Low during configuration, enables pull-up resistors in all I/O pins to respective I/O bank VCCO input. 0: Pull-up during configuration 1: No pull-ups M[2:0] DIN Input Input Mode Select. Selects the FPGA configuration mode. Data Input. M2 = 1, M1 = 1, M0 = 1 Sampled when INIT_B goes High. Serial data provided by host. FPGA captures data on rising CCLK edge. External clock. User I/O User I/O During Configuration Drive at valid logic level throughout configuration. After Configuration User I/O
CCLK
Input
Configuration Clock. If CCLK PCB trace is long or has multiple connections, terminate this output to maintain signal integrity. Initialization Indicator. Active Low. Goes Low at start of configuration during Initialization memory clearing process. Released at end of memory clearing, when mode select pins are sampled. In daisy-chain applications, this signal requires an external 4.7 k pull-up resistor to VCCO_2. FPGA Configuration Done. Low during configuration. Goes High when FPGA successfully completes configuration. Requires external 330 pull-up resistor to 2.5V. Program FPGA. Active Low. When asserted Low for 300 ns or longer, forces the FPGA to restart its configuration process by clearing configuration memory and resetting the DONE and INIT_B pins once PROG_B returns High. Requires external 4.7 k pull-up resistor to 2.5V. If driving externally, use an open-drain or open-collector driver.
User I/O
INIT_B
Open-drain bidirectional I/O
Active during configuration. If CRC error detected during configuration, FPGA drives INIT_B Low.
User I/O
DONE
Open-drain bidirectional I/O
Low indicates that the FPGA is not yet configured.
Pulled High via external pull-up. When High, indicates that the FPGA successfully configured.
PROG_B
Input
Must be High to allow configuration to start.
Drive PROG_B Low and release to reprogram FPGA.
Voltage Compatibility
Most Slave Serial interface signals are within the FPGA's I/O Bank 2, supplied by the VCCO_2 supply input. The VCCO_2 voltage can be 3.3V, 2.5V, or 1.8V to match the requirements of the external host, ideally 2.5V. Using 3.3V or 1.8V requires additional design considerations as the DONE and PROG_B pins are powered by the FPGA's 2.5V VCCAUX supply. See application note XAPP453: "The 3.3V Configuration of Spartan-3 FPGAs" for additional information.
V
Daisy-Chaining
If the application requires multiple FPGAs with different configurations, then configure the FPGAs using a daisy chain, as shown in Figure 61. Use Slave Serial mode (M[2:0] = <1:1:1>) for all FPGAs in the daisy-chain. After the lead FPGA is filled with its configuration data, the lead FPGA passes configuration data via its DOUT output pin to the next FPGA on the falling CCLK edge.
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Functional Description
R
CCLK +1.2V +1.2V
P
Slave Serial Mode
HSWAP
VCCINT VCCO_0 VCCO_2
VCCO_0
P
Slave Serial Mode `1' `1' `1'
HSWAP
VCCINT VCCO_0 VCCO_2
VCCO_0 VCCO_2
V V
Configuration Memory Source
* Internal memory * Disk drive *Over network *Over RF link
VCC CLOCK SERIAL_OUT PROG_B DONE INIT_B GND
CCLK DIN
Spartan-3E FPGA
DOUT INIT_B VCCAUX TDO +2.5V
4.7k
Intelligent V Download Host
`1' `1' `1'
M2 M1 M0
M2 M1 M0
CCLK DIN
Spartan-3E FPGA
DOUT INIT_B VCCAUX TDO +2.5V DOUT
TDI TMS TCK PROG_B GND
PROG_B Recommend open-drain driver +2.5V JTAG TDI TMS TCK TDO
4.7k
330
* Microcontroller *Processor * Tester * Computer
+2.5V DONE
TDI TMS TCK PROG_B GND
DONE
PROG_B DONE INIT_B
TMS TCK
DS312-2_55_022305
Figure 61: Daisy-Chaining using Slave Serial Mode
JTAG Mode
The Spartan-3E FPGA has a dedicated four-wire IEEE 1149.1/1532 JTAG port that is always available any time the FPGA is powered and regardless of the mode pin settings. However, when the FPGA mode pins are set for JTAG mode (M[2:0] = <1:0:1>), the FPGA waits to be configured via the JTAG port after a power-on event or when PROG_B is asserted. Selecting the JTAG mode simply disables the
other configuration modes. No other pins are required as part of the configuration interface. Figure 62 illustrates a JTAG-only configuration interface. The JTAG interface is easily cascaded to any number of FPGAs by connecting the TDO output of one device to the TDI input of the next device in the chain. The TDO output of the last device in the chain loops back to the port connector.
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Functional Description
+1.2V
+1.2V
P
JTAG Mode `1' `0' `1'
VCCINT HSWAP VCCO_0 VCCO_2
VCCO_0 VCCO_2
P
JTAG Mode
VCCINT HSWAP VCCO_0 VCCO_2
VCCO_0 VCCO_2
M2 M1 M0 TDI TMS TCK
Spartan-3E FPGA
VCCAUX TDO +2.5V
`1' `0' `1'
M2 M1 M0 TDI TMS TCK
Spartan-3E FPGA
VCCAUX TDO +2.5V
PROG_B +2.5V JTAG TDI TMS TCK TDO GND
DONE
PROG_B GND
DONE
TMS TCK
DS312-2_56_021405
Figure 62: JTAG Configuration Mode
Voltage Compatibility
The 2.5V VCCAUX supply powers the JTAG interface. All of the user I/Os are separately powered by their respective VCCO_# supplies. When connecting the Spartan-3E JTAG port to a 3.3V interface, the JTAG input pins must be current-limited to 10 mA or less using series resistors. Similarly, the TDO pin is a CMOS output powered from +2.5V. The TDO output can directly drive a 3.3V input but with reduced noise immunity. See application note XAPP453: "The 3.3V Configuration of Spartan-3 FPGAs" for additional information.
or after the PROG_B input is asserted. Power-On Reset (POR) occurs after the VCCINT, VCCAUX, and the VCCO Bank 2 supplies reach their respective input threshold levels. After either a POR or PROG_B event, the three-stage configuration process begins. 1. The FPGA clears (initializes) the internal configuration memory. 2. Configuration data is loaded into the internal memory. 3. The user-application is activated by a start-up process. Figure 63 is a generalized block diagram of the Spartan-3E configuration logic, showing the interaction of different device inputs and Bitstream Generator (BitGen) options. A flow diagram for the configuration sequence of the Serial and Parallel modes appears in Figure 64. Figure 65 shows the Boundary-Scan or JTAG configuration sequence.
Maximum Bitstream Size for Daisy-Chains
The maximum bitstream length supported by Spartan-3E FPGAs in serial daisy-chains is 4,294,967,264 bits (4 Gbits), roughly equivalent to a daisy-chain with 720 XC3S1600E FPGAs. This is a limit only for serial daisy-chains where configuration data is passed via the FPGA's DOUT pin. There is no such limit for JTAG chains.
Initialization
Configuration automatically begins after power-on or after asserting the FPGA PROG_B pin, unless delayed using the FPGA's INIT_B pin. The FPGA holds the open-drain INIT_B signal Low while it clears its internal configuration memory. Externally holding the INIT_B pin Low forces the configuration sequencer to wait until INIT_B again goes High.
Configuration Sequence
The Spartan-3E configuration process is three-stage process that begins after the FPGA powers on (a POR event)
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88
DriveDone
LOCKED
Functional Description
Option
= Bitstream Generator (BitGen) Option
STARTUP
EN
DONE
DONE_cycle
DONE
DCM in User Application
STARTUP_WAIT=TRUE
Option
= Design Attribute
All DCMs
DCMs_LOCKED LCK_cycle
INITIALIZATION
ENABLE
CONFIGURATION
ENABLE
Enable application logic and I/O pins
ENABLE
Power On Reset (POR)
DONE DONE
GTS
Force all I/Os Hi-Z
GTS_cycle
VCCO_2
Clear internal CMOS configuration latches
USER USER
GSR_IN GTS_IN
V CCO2T
Load application data into CMOS configuration latches
CLEARING_MEMORY
POWER_GOOD
RESET
* *
RESET
GSR
Hold all storage elements reset
GWE
VCCINT
WAIT
RESET
WAIT
DonePipe
GWE_cycle
Disable write operations to storage elements
VCCINTT
VCCAUX
V CCAUXT
EN
INIT_B
Figure 63: Generalized Spartan-3E FPGA Configuration Logic Block Diagram
USER_CLOCK JTAG_CLOCK
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PROG_B
Glitch Filter
*
StartupClk
*
These connections are available via the STARTUP_SPARTAN3E library primitive.
CCLK
1 1
TCK
0 0
ConfigRate
INTERNAL_CONFIGURATION_CLOCK
CRC
ENABLE
ERROR
Configuration Error Detection (CRC Checker)
M1
Internal Oscillator
DS312-2_57_022405
M2
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Functional Description
Power-On
Set PROG_B Low after Power-On
VCCINT >1V and VCCAUX > 2V and VCCO Bank 4 > 1V
No
Yes Yes
Clear configuration memory
PROG_B = Low
No
No
INIT_ B = High?
Yes
Sample mode pins
M[2:0] and VS[2:0] pins are sampled on INIT_B rising edge
Load configuration data frames
CRC correct?
No
INIT_B goes Low. Abort Start-Up
Yes Start-Up sequence
DONE pin goes High, signaling end of configuration
User mode
No
Reconfigure?
Yes
DS312-2_58_021404
Figure 64: General Configuration Process
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Power-On
Set PROG_B Low after Power-On
VCCINT >1V and VCCAUX > 2V and VCCO Bank 4 > 1V Load JPROG instruction
No
Yes Clear configuration memory Yes
PROG_B = Low
No No INIT_B = High?
Yes Sample mode pins (JTAG port becomes available)
Load CFG_IN instruction
Load configuration data frames
CRC correct? Yes Synchronous TAP reset (Clock five 1's on TMS)
No
INIT_B goes Low. Abort Start-Up
Load JSTART instruction
Start-Up sequence
User mode
Yes
Reconfigure?
No
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Figure 65: Boundary-Scan Configuration Flow Diagram
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Functional Description
The FPGA signals when the memory-clearing phase is complete by releasing the open-drain INIT_B pin, allowing the pin to go High via the external pull-up resistor to VCCO_2.
Start-Up
At the end of configuration, the Global Set/Reset (GSR) signal is pulsed, placing all flip-flops in a known state. After configuration completes, the FPGA switches over to the user application loaded into the FPGA. The sequence and timing of how the FPGA switches over is programmable as is the clock source controlling the sequence. The default start-up sequence appears in Figure 66, where the Global Three-State signal (GTS) is released one clock cycle after DONE goes High. This sequence allows the DONE signal to enable or disable any external logic used during configuration before the user application in the FPGA starts driving output signals. One clock cycle later, the Global Write Enable (GWE) signal is released. This allows signals to propagate within the FPGA before any clocked storage elements such as flip-flops and block ROM are enabled.
Loading Configuration Data
Configuration data is then written to the FPGA's internal memory. The FPGA holds the Global Set/Reset (GSR) signal active throughout configuration, holding all FPGA flip-flops in a reset state. The FPGA signals when the entire configuration process completes be releasing the DONE pin, allowing it to go High. The FPGA configuration sequence can also be initiated by asserting the PROG_B. Once release, the FPGA begins clearing its internal configuration memory, and progresses through the remainder of the configuration process.
Default Cycles
Start-Up Clock
Phase
0
1
2
3
4
5
67
DONE
GTS
GWE
Sync-to-DONE
Start-Up Clock
Phase
0
1
2
3
4
5
67
DONE High
DONE
GTS
GWE
DS312-2_60_022305
Figure 66: Default Start-Up Sequence
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Functional Description The relative timing of configuration events is programmed via the Bitstream Generator (BitGen) options in the Xilinx development software. For example, the GTS and GWE events can be programmed to wait for all the DONE pins to High on all the devices in a multiple-FPGA daisy-chain, forcing the FPGAs to start synchronously. Similarly, the start-up sequence can be paused at any stage, waiting for selected DCMs to lock to their respective input clock signals. See also Stabilizing DCM Clocks Before User Mode, page 48. The start-up sequence can by synchronized to a clock within the FPGA application using the STARTUP_SPARTAN3E library primitive and by setting the StartupClk bitstream generator option. The FPGA application can optionally assert the Global Set/Reset (GSR) and Global Three-State signal (GTS) signals via the STARTUP_SPARTAN3E primitive.
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Along with the configuration data, it is possible to read back the contents of all registers, distributed RAM, and block RAM resources. This capability is used for real-time debugging. To synchronously control when registers values are captured for readback, using the CAPTURE_SPARTAN3 library primitive, which applies for both Spartan-3 and Spartan-3E FPGA families.
Bitstream Generator (BitGen) Options
Various Spartan-3E FPGA functions are controlled by specific bits in the configuration bitstream image. These values are specified when creating the bitstream image with the Bitstream Generator (BitGen) software. Table 57 provides a list of all BitGen options for Spartan-3E FPGAs.
Readback
Using Slave Parallel mode, configuration data from the FPGA can be read back. Readback is supported only in the Slave Parallel and JTAG modes.
Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options
Option Name ConfigRate Pins/Function Affected CCLK, Configuration Values (default) 3, 6, 12, 25 Description Sets the approximate frequency, in MHz, of the internal oscillator using for Master Serial, SPI, and BPI configuration modes. The internal oscillator powers up at its lowest frequency and the new setting is loaded as part of the configuration bitstream. The software default value is 6 (~6 MHz).
StartupClk
Configuration, Startup
Cclk
Default. The CCLK signal (internally or externally generated) controls the startup sequence when the FPGA transitions from configuration mode to the user mode. See Start-Up, page 91.
A clock signal from within the FPGA application controls the startup sequence when the FPGA transitions from configuration mode to the user mode. See Start-Up, page 91. The FPGA application supplies the user clock on the CLK pin on the STARTUP_SPARTAN3E primitive. The JTAG TCK input controls the startup sequence when the FPGA transitions from configuration mode to the user mode. See Start-Up, page 91.
UserClk
Jtag UnusedPin Unused I/O Pins
Pulldown
Pullup Pullnone
Default. All unused I/O pins have a pull-down resistor to GND.
All unused I/O pins have a pull-up resistor to the VCCO_# supply for its associated I/O bank. All unused I/O pins are left floating (Hi-Z, high-impedance, three-state). Use external pull-up or pull-down resistors or logic to apply a valid signal level. Selects the Configuration Startup phase that activates the FPGA's DONE pin. See Start-Up, page 91.
DONE_cycle
DONE pin, Configuration Startup
1, 2, 3, 4, 5, 6
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Functional Description
Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
Option Name GWE_cycle Pins/Function Affected All flip-flops, LUT RAMs, and SRL16 shift registers, Block RAM, Configuration Startup Values (default) 1, 2, 3, 4, 5, 6 Done Description Selects the Configuration Startup phase that asserts the internal write-enable signal to all flip-flops, LUT RAMs and shift registers (SRL16). It also enables block RAM read and write operations. See Start-Up, page 91. Waits for the DONE pin input to go High before asserting the internal write-enable signal to all flip-flops, LUT RAMs and shift registers (SRL16). Block RAM read and write operations are enabled at this time. Retains the current GWE_cycle setting for partial reconfiguration applications. Selects the Configuration Startup phase that releases the internal three-state control, holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so configured, after this point. See Start-Up, page 91. Waits for the DONE pin input to go High before releasing the internal three-state control, holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so configured, after this point. Retains the current GTS_cycle setting for partial reconfiguration applications. The FPGA does not wait for selected DCMs to lock before completing configuration. If one or more DCMs in the design have the STARTUP_WAIT attribute set to TRUE, the FPGA waits for such DCMs to acquire their respective input clock and assert their LOCKED output. This setting selects the Configuration Startup phase where the FPGA waits for the DCMs to lock. Internally connects a pull-up resistor between DONE pin and VCCAUX. An external 330 pull-up resistor to VCCAUX is still recommended. No internal pull-up resistor on DONE pin. An external 330 pull-up resistor to VCCAUX is required. When configuration completes, the DONE pin stops driving Low and relies on an external 330 pull-up resistor to VCCAUX for a valid logic High. When configuration completes, the DONE pin actively drives High. When using this option, an external pull-up resistor is no longer required. Only one device in an FPGA daisy-chain should use this setting. The input path from DONE pin input back to the Startup sequencer is not pipelined. This option adds a pipeline register stage between the DONE pin input and the Startup sequencer. Used for high-speed daisy-chain configurations when DONE cannot rise in a single CCLK cycle. Releases GWE and GTS signals on the first rising edge of StartupClk after the DONE pin input goes High. Internally connects a pull-up resistor or between PROG_B pin and VCCAUX. An external 4.7 k pull-up resistor to VCCAUX is still recommended. No internal pull-up resistor on PROG_B pin. An external 4.7 k pull-up resistor to VCCAUX is required. Internally connects a pull-up resistor between JTAG TCK pin and VCCAUX. Internally connects a pull-down resistor between JTAG TCK pin and GND. No internal pull-up resistor on JTAG TCK pin. Internally connects a pull-up resistor between JTAG TDI pin and VCCAUX. Internally connects a pull-down resistor between JTAG TDI pin and GND. No internal pull-up resistor on JTAG TDI pin.
Keep GTS_cycle All I/O pins, Configuration 1, 2, 3, 4, 5, 6 Done
Keep LCK_cycle DCMs, Configuration Startup
NoWait
0, 1, 2, 3, 4, 5, 6
DonePin
DONE pin
Pullup
Pullnone
DriveDone
DONE pin
No
Yes
DonePipe
DONE pin
No
Yes
ProgPin
PROG_B pin
Pullup
Pullnone
TckPin
JTAG TCK pin
Pullup
Pulldown Pullnone
TdiPin
JTAG TDI pin
Pullup
Pulldown Pullnone
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Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
Option Name TdoPin Pins/Function Affected JTAG TDO pin Values (default) Description Internally connects a pull-up resistor between JTAG TDO pin and VCCAUX. Internally connects a pull-down resistor between JTAG TDO pin and GND. No internal pull-up resistor on JTAG TDO pin. Internally connects a pull-up resistor between JTAG TMS pin and VCCAUX. Internally connects a pull-down resistor between JTAG TMS pin and GND. No internal pull-up resistor on JTAG TMS pin. The 32-bit JTAG User ID register value is loaded during configuration. The default value is all ones, 0xFFFF_FFFF hexadecimal. To specify another value, enter an 8-character hexadecimal value. Readback and partial reconfiguration are available via the JTAG port or via the SelectMAP interface, if the Persist option is set to Yes. Readback function is disabled. Partial reconfiguration is still available via the JTAG port or via the SelectMAP interface, if the Persist option is set to Yes. Readback function is disabled. Partial reconfiguration is disabled.
Pullup
Pulldown Pullnone
TmsPin
JTAG TMS pin
Pullup
Pulldown Pullnone
UserID
JTAG User ID register JTAG, SelectMAP, Readback, Partial reconfiguration
User string
Security
None
Level1 Level
CRC
Configuration
Enable Disable
Default. Enable CRC checking on the FPGA bitstream. If error detected, FPGA asserts INIT_B Low and DONE pin stays Low.
Turn off CRC checking. All BPI and Slave mode configuration pins are available as user-I/O after configuration. This option is required for Readback and partial reconfiguration using the SelectMAP interface. The SelectMAP interface pins (see Slave Parallel Mode, page 79) are reserved after configuration and are not available as user-I/O.
Persist
SelectMAP interface pins, BPI mode, Slave mode, Configuration
No
Yes
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Functional Description VCCAUX. Each of the four I/O banks has a separate VCCO supply input that powers the output buffers within the associated I/O bank. All of the VCCO connections to a specific I/O bank must be connected and must connect to the same voltage.
Powering Spartan-3E FPGAs
Voltage Supplies
Like Spartan-3 FPGAs, Spartan-3E FPGAs have multiple voltage supply inputs, as shown in Table 58. There are two supply inputs for internal logic functions, VCCINT and
Table 58: Spartan-3E Voltage Supplies
Supply Input VCCINT VCCAUX Description Internal core supply voltage. Supplies all internal logic functions such as CLBs, block RAM, multipliers, etc. Input to Power-On Reset (POR) circuit. Auxiliary supply voltage. Supplies Digital Clock Managers (DCMs), differential drivers, dedicated configuration pins, JTAG interface. Input to Power-On Reset (POR) circuit. Supplies the output buffers in I/O Bank 0, the bank along the top edge of the FPGA. Supplies the output buffers in I/O Bank 1, the bank along the right edge of the FPGA. In Byte-Wide Peripheral Interface (BPI) Parallel Flash Mode, connects to the save voltage as the Flash PROM. Supplies the output buffers in I/O Bank 2 the bank along the bottom edge of the FPGA. Connects to the same voltage as the FPGA configuration source. Input to Power-On Reset (POR) circuit. Supplies the output buffers in I/O Bank 0, the bank along the top edge of the FPGA. Nominal Supply Voltage 1.2V 2.5V
VCCO_0 VCCO_1
Selectable, 3.3V, 3.0V, 2.5V, 1.8, 1.5V, or 1.2V. Selectable, 3.3V, 3.0V, 2.5V, 1.8, 1.5V, or 1.2V. Selectable, 3.3V, 3.0V, 2.5V, 1.8, 1.5V, or 1.2V. Selectable, 3.3V, 3.0V, 2.5V, 1.8, 1.5V, or 1.2V.
VCCO_2
VCCO_3
In a 3.3V-only application, all four VCCO supplies connect to 3.3V. However, Spartan-3E FPGAs provide the ability to bridge between different I/O voltages and standards by applying different voltages to the VCCO inputs of different banks. Refer to I/O Banking Rules for which I/O standards can be intermixed within a single I/O bank. Each I/O bank also has an separate, optional input voltage reference supply, called VREF. If the I/O bank includes an I/O standard that requires a voltage reference such as HSTL or SSTL, then all VREF pins within the I/O bank must be connected to the same voltage.
three-rail regulators specifically designed for Spartan-3 and Spartan-3E FPGAs. The Xilinx Power Corner web site provides links to vendor solution guides and Xilinx power estimation and analysis tools.
Power Distribution System (PDS) Design and Decoupling/Bypass Capacitors
Good power distribution system (PDS) design is important for all FPGA designs, but especially so for high performance applications, greater than 100 MHz. Proper design results in better overall performance, lower clock and DCM jitter, and a generally more robust system. Before designing the printed circuit board (PCB) for the FPGA design, please review XAPP623: "Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors".
Voltage Regulators
Various power supply manufacturers offer complete power solutions for Xilinx FPGAs including some with integrated
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Revision History
The following table shows the revision history for this document. Date 03/01/05 03/21/05 Version 1.0 1.1 Initial Xilinx release. Updated Figure 42. Modified title on Table 33 and Table 39. Revision
The Spartan-3E Family Data Sheet
DS312-1, Spartan-3E FPGA Family: Introduction and Ordering Information (Module 1) DS312-2, Spartan-3E FPGA Family: Functional Description (Module 2) DS312-3, Spartan-3E FPGA Family: DC and Switching Characteristics (Module 3) DS312-4, Spartan-3E FPGA Family: Pinout Descriptions (Module 4)
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Spartan-3E FPGA Family: DC and Switching Characteristics
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DC Electrical Characteristics
In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as follows: Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristics of other families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on characterization. Further changes are not expected. Production: These specifications are approved once the silicon has been characterized over numerous production lots. Parameter values are considered stable with no future changes expected. All parameter limits are representative of worst-case supply voltage and junction temperature conditions. The following applies unless otherwise noted: The parameter values published in this module apply to all SpartanTM-3E devices. AC and DC characteristics are specified using the same numbers for both commercial and industrial grades. If a particular Spartan-3E FPGA differs in functional behavior or electrical characteristic from this data sheet, those differences are described in a separate errata document. The errata documents for Spartan-3E FPGAs are living documents and are available online.
Table 1: Absolute Maximum Ratings
Symbol VCCINT VCCAUX VCCO VREF VIN(2) Description Internal supply voltage Auxiliary supply voltage Output driver supply voltage Input reference voltage Voltage applied to all User I/O pins and Dual-Purpose pins Voltage applied to all Dedicated pins VESD Electrostatic Discharge Voltage Human body model Charged device model Machine model TJ TSTG Notes:
1. 2. 3. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability. As a rule, the VIN limits apply to both the DC and AC components of signals. Simple application solutions are available that show how to handle overshoot/undershoot as well as achieve PCI compliance. Refer to the following application notes: "VirtexTM-II Pro and Spartan-3 3.3V PCI Reference Design" (XAPP653) and "Using 3.3V I/O Guidelines in a Virtex-II Pro Design" (XAPP659). Each of the User I/O and Dual-Purpose pins is associated with one of the four banks' VCCO rails. Meeting the VIN max limit ensures that the internal diode junctions that exist between these pins and their associated VCCO rails do not turn on. Table 4 specifies the VCCO range used to determine the max limit. When VCCO is at its maximum recommended operating level (3.45V), VIN max is 3.95V. The maximum voltage that avoids oxide stress is VINX = 4.05V. As long as the VIN max specification is met, oxide stress is not possible. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail (2.5V). Meeting the VIN max limit ensures that the internal diode junctions that exist between each of these pins and the VCCAUX rail do not turn on. Table 4 specifies the VCCAUX range used to determine the max limit. When VCCAUX is at its maximum recommended operating level (2.625V), VIN max < 3.125V. As long as the VIN max specification is met, oxide stress is not possible. For soldering guidelines, see "Device Packaging and Thermal Characteristics" at www.xilinx.com/bvdocs/userguides/ug112.pdf. Also see "Implementation and Solder Reflow Guidelines for Pb-Free Packages" at www.xilinx.com/bvdocs/appnotes/xapp427.pdf.
Conditions
Min -0.5 -0.5 -0.5 -0.5
Max 1.32 3.00 3.75 VCCO + 0.5(3) VCCO + 0.5(3)
Units V V V V V V V V V C C
Driver in a high-impedance state
-0.5 -0.5 -2000 -500 -200 -65
VCCAUX + 0.5(4) +2000 +500 +200 125 150
Junction temperature Storage temperature
4.
5.
(c) 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.
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Table 2: Supply Voltage Thresholds for Power-On Reset
Symbol VCCINTT VCCAUXT VCCO2T
Notes:
1. 2. VCCINT, VCCAUX, and VCCO supplies may be applied in any order. To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with no dips at any point.
Description Threshold for the VCCINT supply Threshold for the VCCAUX supply Threshold for the VCCO Bank 2 supply
Min 0.4 0.8 0.4
Max 1.0 2.0 1.0
Units V V V
Table 3: Power Voltage Levels Necessary for Preserving RAM Contents
Symbol VDRINT VDRAUX VDRO
Notes:
1. RAM contents include configuration data.
Description VCCINT level required to retain RAM data VCCAUX level required to retain RAM data VCCO level required to retain RAM data
Min 1.0 2.0 1.0
Units V V V
Table 4: General Recommended Operating Conditions
Symbol TJ Description Junction temperature Commercial Industrial VCCINT VCCO (1) VCCAUX (2)
Notes:
1. 2. The VCCO range given here spans the lowest and highest operating voltages of all supported I/O standards. The recommended VCCO range specific to each of the single-ended I/O standards is given in Table 7, and that specific to the differential standards is given in Table 9. Only during DCM operation, it is recommended that the rate of change of VCCAUX not exceed 10 mV/ms.
Min 0 -40 1.140 1.140 2.375
Nom 1.200 2.500
Max 85 100 1.260 3.450 2.625
Units C C V V V
Internal supply voltage Output driver supply voltage Auxiliary supply voltage
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DC and Switching Characteristics
Table 5: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
Symbol IL(2) IRPU(3) Description Leakage current at User I/O, Dual-Purpose, and Dedicated pins Current through pull-up resistor at User I/O, Dual-Purpose, and Dedicated pins Test Conditions Driver is in a high-impedance state, VIN = 0V or VCCO max, sample-tested VIN = 0V, VCCO = 3.3V VIN = 0V, VCCO = 3.0V VIN = 0V, VCCO = 2.5V VIN = 0V, VCCO = 1.8V VIN = 0V, VCCO = 1.5V VIN = 0V, VCCO = 1.2V IRPD(3) Current through pull-down resistor at User I/O, Dual-Purpose, and Dedicated pins VREF current per pin Input capacitance VIN = VCCO Min -10 Typ Max +10 Units A mA mA mA mA mA mA mA
IREF CIN
Notes:
1. 2.
All VCCO levels
-10 3
-
+10 10
A pF
3.
The numbers in this table are based on the conditions set forth in Table 4. The IL specification applies to every I/O pin throughout power-on as long as the voltage on that pin stays between the absolute VIN minimum and maximum values (Table 1). For hot-swap applications, at the time of card connection, be sure to keep all I/O voltages within this range before applying VCCO power. Also consider applying VCCO power before the connection of data lines occurs. When the FPGA is completely unpowered, the impedance at the I/O pins is high. This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD.
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Table 6: Quiescent Supply Current Characteristics
Symbol ICCINTQ Description Quiescent VCCINT supply current Device XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E ICCOQ Quiescent VCCO supply current XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E ICCAUXQ Quiescent VCCAUX supply current XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E
Notes:
1. The numbers in this table are based on the conditions set forth in Table 4. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. For typical values, the ambient temperature (TA) is 25C with VCCINT = 1.2V, VCCO = 2.5V, and VCCAUX = 2.5V. The FPGA is programmed with a "blank" configuration data file (i.e., a design with no functional elements instantiated). For conditions other than those described above, (e.g., a design including functional elements), measured quiescent current levels may be higher than the values in the table. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3E Web Power Tool, a future web-based application, provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower, which will be included in a future release of the Xilinx development software, takes a netlist as input to provide more accurate maximum and typical estimates. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully. All typical quiescent current values are early estimates.
Typ(4) 15 38 68 98 108 1.0 1.5 1.7 1.8 2.2 10 15 25 35 45
Max
Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2.
3. 4.
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Table 7: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
IOSTANDARD Attribute HSTL_I_18 HSTL_III_18 LVCMOS12(4) LVCMOS15(4) LVCMOS18(4) LVCMOS25(4,5) LVCMOS33(4) LVTTL PCI33_3(7) PCI66_3(7) PCIX(7) SSTL18_I SSTL2_I
Notes:
1. Descriptions of the symbols used in this table are as follows:
VCCO -- the supply voltage for output drivers VREF -- the reference voltage for setting the input switching threshold VIL -- the input voltage that indicates a Low logic level VIH -- the input voltage that indicates a High logic level
VCCO for Drivers(2) Min (V) 1.7 1.7 1.1 1.4 1.65 2.3 3.0 3.0 1.70 2.3 Nom (V) 1.8 1.8 1.2 1.5 1.8 2.5 3.3 3.3 3.0 3.0 TBD 1.80 2.5 Max (V) 1.9 1.9 1.3 1.6 1.95 2.7 3.45 3.45 1.90 2.7 Min (V) 0.8 0.833 1.15
VREF Nom (V) 0.9 1.1 0.900 1.25 Max (V) 1.1 0.969 1.35
VIL Max (V) VREF - 0.1 VREF - 0.1 0.38 0.38 0.38 0.7 0.8 0.8 0.9 0.9 TBD VREF - 0.125 VREF - 0.15
VIH Min (V) VREF + 0.1 VREF + 0.1 0.8 0.8 0.8 1.7 2.0 2.0 1.5 1.5 TBD VREF + 0.125 VREF + 0.15
2. 3. 4. 5.
6. 7.
The VCCO rails supply only output drivers, not input circuits. For device operation, the maximum signal voltage (VIH max) may be as high as VIN max. See Table 1. There is approximately 100 mV of hysteresis on inputs using any LVCMOS standard. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) use the LVCMOS25 standard and draw power from the VCCAUX rail (2.5V). The Dual-Purpose configuration pins use the LVCMOS25 standard before the User mode. When using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the VCCO lines of Banks 0, 1, and 2 at power-on as well as throughout configuration. The Global Clock Inputs (GCLK0-GCLK15, RHCLK0-RHCLK7, and LHCLK0-LHCLK7) are Dual-Purpose pins to which any signal standard may be assigned. For more information, see "Virtex-II Pro and Spartan-3 3.3V PCI Reference Design" (XAPP653).
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Table 8: DC Characteristics of User I/Os Using Single-Ended Standards
Test Conditions IOL IOSTANDARD Attribute HSTL_I_18 HSTL_III_18 LVCMOS12(3) LVCMOS15(3) 2 2 4 6 LVCMOS18(3) 2 4 6 8 LVCMOS25(3,4) 2 4 6 8 12 LVCMOS33(3) 2 4 6 8 12 16 LVTTL(3) 2 4 6 8 12 16 PCI33_3(5) PCI66_3(5) PCIX SSTL18_I (mA) 8 24 2 2 4 6 2 4 6 8 2 4 6 8 12 2 4 6 8 12 16 2 4 6 8 12 16 1.5 1.5 TBD 6.7 IOH (mA) -8 -8 -2 -2 -4 -6 -2 -4 -6 -8 -2 -4 -6 -8 -12 -2 -4 -6 -8 -12 -16 -2 -4 -6 -8 -12 -16 -0.5 -0.5 TBD -6.7 0.10VCCO 0.10VCCO TBD VTT - 0.475 0.90VCCO 0.90VCCO TBD VTT + 0.475 0.4 2.4 0.4 VCCO - 0.4 0.4 VCCO - 0.4 0.4 VCCO - 0.4 Logic Level Characteristics VOL Max (V) 0.4 0.4 0.4 0.4 VOH Min (V) VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4
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Table 8: DC Characteristics of User I/Os Using Single-Ended Standards (Continued)
Test Conditions IOL IOSTANDARD Attribute SSTL2_I
Notes:
1. 2. The numbers in this table are based on the conditions set forth in Table 4 and Table 7. Descriptions of the symbols used in this table are as follows:
IOL -- the output current condition under which VOL is tested IOH -- the output current condition under which VOH is tested VOL -- the output voltage that indicates a Low logic level VOH -- the output voltage that indicates a High logic level VIL -- the input voltage that indicates a Low logic level VIH -- the input voltage that indicates a High logic level VCCO -- the supply voltage for output drivers VREF -- the reference voltage for setting the input switching threshold VTT -- the voltage applied to a resistor termination
Logic Level Characteristics IOH (mA) -8.1 VOL Max (V) VTT - 0.61 VOH Min (V) VTT + 0.61
(mA) 8.1
3. 4.
5.
For the LVCMOS and LVTTL standards: the same VOL and VOH limits apply for both the Fast and Slow slew attributes. All Dedicated output pins (DONE and TDO) as well as Dual-Purpose totem-pole output pins (CCLK, D0-D7, BUSY/DOUT, CSO_B, MOSI, HDC, LDC0-LDC2, and A0-A23) exhibit the characteristics of LVCMOS25 with Slow slew rate; all have 8 mA drive except CCLK, which has 12 mA drive. Tested according to the relevant PCI specifications. For more information, see "Virtex-II Pro and Spartan-3 3.3V PCI Reference Design" (XAPP653).
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VINP Internal Logic VINN
P N
Differential I/O Pair Pins
VINN VINP GND level
50%
VICM
VID
VICM = Input common mode voltage =
VINP + VINN 2
VID = Differential input voltage = VINP - VINN
DS099-3_01_012304
Figure 1: Differential Input Voltages
Table 9: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
VCCO for Drivers(1) VID Min (mV) 100 100 200 100 2.625 100 Nom (mV) 350 350 800 200 Max (mV) 600 600 600 1000 Min (V) 0.30 0.30 0.30 0.3 0.3 VICM Nom (V) 1.25 1.25 1.2 1.20 Max (V) 2.20 2.20 2.2 2.2 1.4 0.8 2.0 0.5 1.7 Min (V) VIH Max (V) Min (V) VIL Max (V) -
IOSTANDARD Attribute
LVDS_25 BLVDS_25 MINI_LVDS_25 LVPECL_25(2) RSDS_25 Notes:
1. 2. 3.
Min (V) 2.375 2.375 2.375
Nom (V) 2.50 2.50 2.50 Inputs Only
Max (V) 2.625 2.625 2.625
2.375
2.50
The VCCO rails supply only differential output drivers, not input circuits. Spartan-3E devices support this standard for inputs only, not for outputs. VREF inputs are not used for any of the differential I/O standards.
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VOUTP Internal Logic VOUTN
P N
Differential I/O Pair Pins
VOUTN VOUTP GND level
50%
VOH VOD VOCM
VOL
VOCM = Output common mode voltage =
VOUTP + VOUTN
2 VOD = Output differential voltage = VOUTP - VOUTN
VOH = Output voltage indicating a High logic level VOL = Output voltage indicating a Low logic level
DS312-3_03_021505
Figure 2: Differential Output Voltages
Table 10: DC Characteristics of User I/Os Using Differential Signal Standards
VOD IOSTANDARD Attribute LVDS_25 BLVDS_25 MINI_LVDS_25 RSDS_25 Notes:
1. 2. 3. The numbers in this table are based on the conditions set forth in Table 4 and Table 9. Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100 across the N and P pins of the differential signal pair. At any given time, no more than two differential standards may be assigned to each bank.
VOD Max (mV) 450 450 600 400 Min (mV) Max (mV) 50 Min (V) 1.125 1.0 1.1
VOCM Typ (V) Max (V) 1.20 1.375 1.4 1.4
VOCM Min (mV) Max (mV) 50 -
VOH Min (V) 1.25 1.15 1.15
VOL Max (V) 1.25 1.25 1.35
Min (mV) 250 250 300 100
Typ (mV) 350 350 -
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Switching Characteristics
All Spartan-3E FPGAs ship in two speed grades: -4 and the higher performance -5. Switching characteristics in this document may be designated as Advance, Preliminary, or Production, as shown in Table 11. Each category is defined as follows: Advance: These specifications are based on simulations only and are typically available soon after establishing FPGA specifications. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Preliminary: These specifications are based on complete early silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting preliminary delays is greatly reduced compared to Advance data. Production: These specifications are approved once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. Production-quality systems must use FPGA designs compiled using a speed file designated as Production status. FPGAs designs using a less mature speed file designation should only be used during system prototyping or pre-production qualification. FPGA designs with speed files designated as Preview, Advance, or Preliminary should not be used in a production-quality system. Whenever a speed file designation changes, as a device matures toward Production status, Xilinx recommends rerunning the Xilinx ISE software on the FPGA design. This ensures that the FPGA design incorporates the latest timing information and software updates. All specified limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise noted, the following applies: Parameter values apply to all Spartan-3E devices. All parameters representing voltages are measured with respect to GND. Timing parameters and their representative values are selected for inclusion below either because they are important as general design requirements or they indicate fundamental device performance characteristics. The Spartan-3E speed files (v1.10), part of the Xilinx Development Software, are the original source for many but not all of the values. The speed grade designations for these files are shown in Table 11. For more complete, more precise, and worst-case data, use the values reported by the Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to the simulation netlist.
Table 11: Spartan-3E v1.10 Speed Grade Designations
Device XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E Preview -4 -4 -4 -4 -4 Advance Preliminary Production
System Usage
Prototyping Only
Production
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS). Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table 12 and Table 13) apply to any application that only employs the DLL component. When the DFS and/or the PS components are used together with the DLL, then the specifications listed in the DFS and PS tables supersede any corresponding ones in the DLL tables. (See Table 14 and Table 15 for the DFS; tables for the PS are not yet available.) DLL specifications that do not change with the addition of DFS or PS functions are presented in Table 12 and Table 13. All DCM clock output signals exhibit an approximate duty cycle of 50%. Period jitter and cycle-cycle jitter are two (of many) different ways of characterizing clock jitter. Both specifications describe statistical variation from a mean value. Period jitter is the worst-case deviation from the average clock period of all clock cycles in the collection of clock periods sampled (usually from 100,000 to more than a million samples for specification purposes). In a histogram of period jitter, the mean value is the clock period. Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods sampled. In a histogram of cycle-cycle jitter, the mean value is zero.
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Table 12: Recommended Operating Conditions for the DLL
Speed Grade -5 Symbol Input Frequency Ranges FCLKIN Notes:
1. 2. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use. Use of the DFS permits lower FCLKIN frequencies. See Table 14.
-4 Max Min Max Units
Description
Min
CLKIN_FREQ_DLL
Frequency for the CLKIN input
5
326
5(2)
280
MHz
Table 13: Switching Characteristics for the DLL
Speed Grade -5 Symbol Output Frequency Ranges CLKOUT_FREQ_1X Frequency for the CLK0 and CLK180 outputs Frequency for the CLK90 and CLK270 outputs CLKOUT_FREQ_2X Notes:
1. 2. The numbers in this table are based on the operating conditions set forth in Table 4 and Table 12. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
-4 Max Min Max Units
Description
Min
5 5 10
326 165 400
5 5 10
280 165 330
MHz MHz MHz
Frequency for the CLK2X and CLK2X180 outputs
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Table 14: Recommended Operating Conditions for the DFS
Speed Grade -5 Symbol Input Frequency Ranges(2) FCLKIN Notes:
1. 2. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are in use. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 12.
-4 Max 326 Min 0.2 Max 326 Units MHz
Description Frequency for the CLKIN input
Min 0.2
CLKIN_FREQ_FX
Table 15: Switching Characteristics for the DFS
Speed Grade -5 Symbol Output Frequency Ranges CLKOUT_FREQ_FX Notes:
1. 2. The numbers in this table are based on the operating conditions set forth in Table 4 and Table 14. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) is in use.
-4 Max 326 Min 5 Max 280 Units MHz
Description Frequency for the CLKFX and CLKFX180 outputs
Min 5
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Configuration and JTAG Timing
VCCINT (Supply) VCCAUX (Supply) VCCO Bank 2 (Supply) PROG_B (Input) INIT_B (Open-Drain) CCLK (Output)
DS312-3_01_020505
1.2V 1.0V 2.5V 2.0V
1.0V TPOR
TPROG
TPL
TICCK
Notes:
1. 2. 3. The VCCINT, VCCAUX, and VCCO supplies may be applied in any order. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 3: Waveforms for Power-On and the Beginning of Configuration Table 16: Power-On Timing and the Beginning of Configuration
All Speed Grades Symbol TPOR(2) Description The time from the application of VCCINT, VCCAUX, and VCCO Bank 2 supply voltage ramps (whichever occurs last) to the rising transition of the INIT_B pin Device XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E TPROG TPL
(2)
Min 0.3 0.5
Max 5 5 5 5 7 2 2 2 2 3 4.0
Units ms ms ms ms ms s ms ms ms ms ms s
The width of the low-going pulse on the PROG_B pin The time from the rising edge of the PROG_B pin to the rising transition on the INIT_B pin
All XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E
TICCK(3)
The time from the rising edge of the INIT_B pin to the generation of the configuration clock signal at the CCLK output pin
All
Notes:
1. 2. 3. The numbers in this table are based on the operating conditions set forth in Table 4. This means power must be applied to all VCCINT, VCCO, and VCCAUX lines. Power-on reset and the clearing of configuration memory occurs during this period. This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes.
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PROG_B (Input)
INIT_B (Open-Drain) TCCL CCLK (Input/Output) TDCC DIN (Input) TCCD Bit 0 Bit 1 1/FCCSER Bit n Bit n+1 TCCO DOUT (Output) Bit n-64 Bit n-63
DS099-3_04_071604
TCCH
Figure 4: Waveforms for Master and Slave Serial Configuration Table 17: Timing for the Master and Slave Serial Configuration Modes
Slave/ Master All Speed Grades Min Max Units
Symbol Clock-to-Output Times TCCO
Description
The time from the falling transition on the CCLK pin to data appearing at the DOUT pin
Both
1.5
12.0
ns
Setup Times TDCC The time from the setup of data at the DIN pin to the rising transition at the CCLK pin Both 10.0 ns
Hold Times TCCD The time from the rising transition at the CCLK pin to the point when data is last held at the DIN pin Both 0 ns
Clock Timing TCCH TCCL FCCSER FCCSER
Notes:
1. 2. The numbers in this table are based on the operating conditions set forth in Table 4. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
The High pulse width at the CCLK input pin The Low pulse width at the CCLK input pin Frequency of the clock signal at the CCLK input pin No bitstream compression With bitstream compression
Slave
5.0 5.0 -
66(2) 20 +50%
ns ns MHz MHz -
Variation from the CCLK output frequency set using the ConfigRate BitGen option
Master
-50%
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PROG_B (Input)
INIT_B (Open-Drain) TSMCSCC CS_B (Input) TSMCCW RDWR_B (Input) TCCH CCLK (Input) TSMDCC D0 - D7 (Inputs) TSMCCD 1/FCCPAR TCCL TSMWCC TSMCCCS
Byte 0
Byte 1 TSMCKBY
Byte n TSMCKBY
Byte n+1
BUSY (Output)
High-Z BUSY
High-Z
DS312-3_02_020805
Notes:
1. It is possible to abort configuration by pulling CS_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent cycle for which CS_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B switches High, be careful to avoid contention on the D0 - D7 bus.
Figure 5: Waveforms for Slave Parallel Configuration
Table 18: Timing for the Slave Parallel Configuration Mode
All Speed Grades Symbol Clock-to-Output Times TSMCKBY Setup Times TSMDCC TSMCSCC TSMCCW(2) The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin The time from the setup of a logic level at the CS_B pin to the rising transition at the CCLK pin The time from the setup of a logic level at the RDWR_B pin to the rising transition at the CCLK pin 10.0 10.0 10.0 ns ns ns The time from the rising transition on the CCLK pin to a signal transition at the BUSY pin 12.0 ns Description Min Max Units
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Table 18: Timing for the Slave Parallel Configuration Mode (Continued)
All Speed Grades Symbol Hold Times TSMCCD TSMCCCS TSMWCC Clock Timing TCCH TCCL FCCPAR The High pulse width at the CCLK input pin The Low pulse width at the CCLK input pin Frequency of the clock signal at the CCLK input pin No bitstream compression Not using the BUSY pin(2) Using the BUSY pin 5 5 50 66 20 ns ns MHz MHz MHz The time from the rising transition at the CCLK pin to the point when data is last held at the D0-D7 pins The time from the rising transition at the CCLK pin to the point when a logic level is last held at the CS_B pin The time from the rising transition at the CCLK pin to the point when a logic level is last held at the RDWR_B pin 0 0 0 ns ns ns Description Min Max Units
With bitstream compression
Notes:
1. 2. 3.
The numbers in this table are based on the operating conditions set forth in Table 4. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification. Some Xilinx documents may refer to Parallel modes as "SelectMAP" modes.
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TCCH
TCCL
TCK (Input)
TTMSTCK TTCKTMS 1/FTCK
TMS (Input)
TTDITCK TTCKTDI
TDI (Input)
TTCKTDO
TDO (Output)
DS099_06_040703
Figure 6: JTAG Waveforms
Table 19: Timing for the JTAG Test Access Port
All Speed Grades Symbol Clock-to-Output Times TTCKTDO Setup Times TTDITCK TTMSTCK Hold Times TTCKTDI TTCKTMS The time from the rising transition at the TCK pin to the point when data is last held at the TDI pin The time from the rising transition at the TCK pin to the point when a logic level is last held at the TMS pin 0 0 ns ns The time from the setup of data at the TDI pin to the rising transition at the TCK pin The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin 7.0 7.0 ns ns The time from the falling transition on the TCK pin to data appearing at the TDO pin 1.0 11.0 ns Description Min Max Units
Clock Timing TCCH TCCL FTCK
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4.
The High pulse width at the TCK pin The Low pulse width at the TCK pin Frequency of the TCK signal
5 5 -
33
ns ns MHz
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Revision History
The following table shows the revision history for this document. Date 03/01/05 Version 1.0 Initial Xilinx release. Revision
The Spartan-3E Family Data Sheet
DS312-1, Spartan-3E FPGA Family: Introduction and Ordering Information (Module 1) DS312-2, Spartan-3E FPGA Family: Functional Description (Module 2) DS312-3, Spartan-3E FPGA Family: DC and Switching Characteristics (Module 3) DS312-4, Spartan-3E FPGA Family: Pinout Descriptions (Module 4)
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0 0
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Advance Product Specification
Introduction
This section describes the various pins on a SpartanTM-3E FPGA and how they connect within the supported component packages.
Pin Types
A majority of the pins on a Spartan-3E FPGA are general-purpose, user-defined I/O pins. There are, however, up to 11 different functional types of pins on Spartan-3E packages, as outlined in Table 1. In the package footprint drawings that follow, the individual pins are color-coded according to pin type as in the table.
Table 1: Types of Pins on Spartan-3E FPGAs
Type / Color Code I/O INPUT DUAL Description Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form differential I/Os. Unrestricted, general-purpose input-only pin. This pin does not have an output structure. Dual-purpose pin used in some configuration modes during the configuration process and then usually available as a user I/O after configuration. If the pin is not used during configuration, this pin behaves as an I/O-type pin. Some of the dual-purpose pins are also global or edge clock inputs (GCLK). Pin Name(s) in Type IO IO_Lxxy_# IP IP_Lxxy_# M[2:0] HSWAP CCLK MOSI/CSI_B D[7:1] D0/DIN CSO_B RDWR_B BUSY/DOUT INIT_B A[23:20] A19/VS2 A18/VS1 A17/VS0 A[16:0] LDC[2:0] HDC IP/VREF_# IP_Lxx_#/VREF_#
VREF
Dual-purpose pin that is either a user-I/O pin or, along with all other VREF pins in the same bank, provides a reference voltage input for certain I/O standards. If used for a reference voltage within a bank, all VREF pins within the bank must be connected. Either a user-I/O pin or an input to a specific clock buffer driver. Every package has 16 global clock inputs that optionally clock the entire device. The RHCLK inputs optionally clock the right-hand side of the device. The LHCLK inputs optionally clock the left-hand side of the device. Some of the clock pins are shared with the dual-purpose configuration pins and are considered DUAL-type. Dedicated configuration pin. Not available as a user-I/O pin. Every package has two dedicated configuration pins. These pins are powered by VCCAUX.
GCLK LHCLK RHCLK
GCLK[15:0], LHCLK[7:0], RHCLK[7:0]
CONFIG
DONE, PROG_B
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Table 1: Types of Pins on Spartan-3E FPGAs
Type / Color Code JTAG GND VCCAUX VCCINT VCCO Description Dedicated JTAG pin. Not available as a user-I/O pin. Every package has four dedicated JTAG pins. These pins are powered by VCCAUX. Dedicated ground pin. The number of GND pins depends on the package used. All must be connected. Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the package used. All must be connected to +2.5V. Dedicated internal core logic power supply pin. The number of VCCINT pins depends on the package used. All must be connected to +1.2V. Along with all the other VCCO pins in the same bank, this pin supplies power to the output buffers within the I/O bank and sets the input threshold voltage for some I/O standards. This package pin is not connected in this specific device/package combination but may be connected in larger devices in the same package. Pin Name(s) in Type TDI, TMS, TCK, TDO GND VCCAUX VCCINT VCCO_#
N.C.
Notes:
1.
N.C.
# = I/O bank number, an integer between 0 and 3.
I/Os with Lxxy_# are part of a differential output pair. `L' indicates differential output capability. The "xx" field is a two-digit integer, unique to each bank that identifies a differential pin-pair. The `y' field is either `P' for the true signal or `N' for the inverted signal in the differential pair. The `#' field is the I/O bank number.
significance. Figure 1 provides a specific example showing a differential input to and a differential output from Bank 1. `L' indicates that the pin is part of a differentiaL pair. "xx" is a two-digit integer, unique for each bank, that identifies a differential pin-pair. `y' is replaced by `P' for the true signal or `N' for the inverted. These two pins form one differential pin-pair. `#' is an integer, 0 through 3, indicating the associated I/O bank.
Differential Pair Labeling
A pin supports differential standards if the pin is labeled in the format "Lxxy_#". The pin name suffix has the following
Pair Number
Bank 0 IO_L38P_1
Bank Number
Bank 1
Bank 3
IO_L38N_1 IO_L39P_1 IO_L39N_1
Positive Polarity, True Driver
Spartan-3E FPGA Bank 2
Negative Polarity, Inverted Driver
DS312-4_00_022305
Figure 1: Differential Pair Labeling
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Pinout Descriptions mechanical dimensions of the standard and Pb-free packages are similar, as shown in the mechanical drawings provided in Table 4. Not all Spartan-3E densities are available in all packages. For a specific package, however, there is a common footprint that supports all the devices available in that package. See the footprint diagrams that follow.
Package Overview
Table 2 shows the eight low-cost, space-saving production package styles for the Spartan-3E family. Each package style is available as a standard and an environmentally-friendly lead-free (Pb-free) option. The Pb-free packages include an extra `G' in the package style name. For example, the standard "VQ100" package becomes "VQG100" when ordered as the Pb-free option. The
Table 2: Spartan-3E Family Package Options
Package VQ100 / VQG100 CP132 / CPG132 TQ144 / TQG144 PQ208 / PQG208 FT256 / FTG256 FG320 / FGG320 FG400 / FGG400 FG484 / FGG484 Leads 100 132 144 208 256 320 400 484 Type Very-thin Quad Flat Pack (VQFP) Chip-Scale Package (CSP) Thin Quad Flat Pack (TQFP) Plastic Quad Flat Pack (PQFP) Fine-pitch, Thin Ball Grid Array (FBGA) Fine-pitch Ball Grid Array (FBGA) Fine-pitch Ball Grid Array (FBGA) Fine-pitch Ball Grid Array (FBGA) Maximum I/O 66 92 108 158 190 250 304 376 Pitch (mm) 0.5 0.5 0.5 0.5 1.0 1.0 1.0 1.0 Area (mm) 16 x 16 8x8 22 x 22 30.6 x 30.6 17 x 17 19 x 19 21 x 21 23 x 23 Height (mm) 1.20 1.10 1.60 4.10 1.55 2.00 2.60 2.60
Selecting the Right Package Option
Spartan-3 FPGAs are available in both quad-flat pack (QFP) and ball grid array (BGA) packaging options. While QFP packaging offers the lowest absolute cost, the BGA
packages are superior in almost every other aspect, as summarized in Table 3. Consequently, Xilinx recommends using BGA packaging whenever possible.
Table 3: QFP and BGA Comparison
Characteristic Maximum User I/O Packing Density (Logic/Area) Signal Integrity Simultaneous Switching Output (SSO) Support Thermal Dissipation Minimum Printed Circuit Board (PCB) Layers Hand Assembly/Rework Quad Flat Pack (QFP) 158 Good Fair Limited Fair 4 Possible Ball Grid Array (BGA) 376 Better Better Better Better 6 Difficult
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Mechanical Drawings
Detailed mechanical drawings for each package type are available from the Xilinx website at the specified location in Table 4.
Table 4: Xilinx Package Mechanical Drawings
Package VQ100 / VQG100 CP132 / CPG132 TQ144 / TQG144 PQ208 / PQG208 FT256 / FTG256 FG320 / FGG320 FG400 / FGG400 FG484 / FGG484 Web Link (URL) http://www.xilinx.com/bvdocs/packages/vq100.pdf http://www.xilinx.com/bvdocs/packages/cp132.pdf http://www.xilinx.com/bvdocs/packages/tq144.pdf http://www.xilinx.com/bvdocs/packages/pq208.pdf http://www.xilinx.com/bvdocs/packages/ft256.pdf http://www.xilinx.com/bvdocs/packages/fg320.pdf http://www.xilinx.com/bvdocs/packages/fg400.pdf http://www.xilinx.com/bvdocs/packages/fg484.pdf A majority of package pins are user-defined I/O or input pins. However, the numbers and characteristics of these I/O depend on the device type and the package in which it is available, as shown in Table 6. The table shows the maximum number of single-ended I/O pins available, assuming that all I/O-, INPUT-, DUAL-, VREF-, and GCLK-type pins are used as general-purpose I/O. Likewise, the table shows the maximum number of differential pin-pairs available on the package. Finally, the table shows how the total maximum user-I/Os are distributed by pin type, including the number of unconnected--i.e., N.C.--pins on the device.
Package Pins by Type
Each package has three separate voltage supply inputs--VCCINT, VCCAUX, and VCCO--and a common ground return, GND. The numbers of pins dedicated to these functions vary by package, as shown in Table 5.
Table 5: Power and Ground Supply Pins by Package
Package VQ100 CP132 TQ144 PQ208 FT256 FG320 FG400 FG484 VCCINT 4 6 4 4 8 8 16 16 VCCAUX 4 4 4 8 8 8 8 10 VCCO 8 8 9 12 16 20 24 28 GND 12 16 13 20 28 28 42 48
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Table 6: Maximum User I/O by Package
Maximum User I/Os 66 VQ100 XC3S250E XC3S250E CP132 XC3S500E XC3S100E TQ144 XC3S250E XC3S250E PQ208 XC3S500E XC3S250E XC3S500E XC3S1200E XC3S500E XC3S1200E XC3S1600E XC3S1200E FG400 XC3S1600E XC3S1600E FG484 304 376 124 156 156 214 62 72 46 46 24 28 16 16 0 0 FG320 FT256 158 172 190 190 232 250 250 304 65 68 77 77 92 99 99 124 58 62 76 78 102 120 119 156 25 33 33 31 48 47 48 62 46 46 46 46 46 46 46 46 13 15 19 19 20 21 21 24 16 16 16 16 16 16 16 16 0 16 0 0 18 0 0 0 108 158 40 65 20 58 21 25 42 46 9 13 16 16 0 0 92 108 41 40 22 22 0 19 46 42 8 9 16 16 0 0 66 92 30 41 16 22 1 0 21 46 4 8 24 16 0 0 Maximum Differential Pairs 30 All Possible I/Os by Type I/O 16 INPUT 1 DUAL 21 VREF 4 GCLK 24 N.C. 0
Device XC3S100E
Package
Electronic versions of the package pinout tables and footprints are available for download from the Xilinx web site. Download the files from the following location: Using a spreadsheet program, the data can be sorted and reformat-
ted according to any specific needs. Similarly, the ASCII-text file is easily parsed by most scripting programs. http://www.xilinx.com/bvdocs/publications/s3e_pin.zip
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VQ100: 100-lead Very-thin Quad Flat Package
The XC3S100E and the XC3S250E devices are available in the 100-lead very-thin quad flat package, VQ100. Both devices share a common footprint for this package as shown in Table 7 and Figure 2. Table 7 lists all the package pins. They are sorted by bank number and then by pin name of the largest device. Pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier. The VQ100 package does not support the Byte-wide Peripheral Interface (BPI) configuration mode. Consequently, the VQ100 footprint has fewer DUAL-type pins than other packages. An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx web site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Table 7: VQ100 Package Pinout
XC3S100E XC3S250E Pin Name VCCO_0 IO_L01N_1 IO_L01P_1 IO_L02N_1 IO_L02P_1 IO_L03N_1/RHCLK1 IO_L03P_1/RHCLK0 IO_L04N_1/RHCLK3 IO_L04P_1/RHCLK2 IO_L05N_1/RHCLK5 IO_L05P_1/RHCLK4 IO_L06N_1/RHCLK7 IO_L06P_1/RHCLK6 IO_L07N_1 IO_L07P_1 IP/VREF_1 VCCO_1 VCCO_1 IO/D5 IO/M1 IO_L01N_2/INIT_B IO_L01P_2/CSO_B IO_L02N_2/MOSI/CSI_B IO_L02P_2/DOUT/BUSY IO_L03N_2/D6/GCLK13 IO_L03P_2/D7/GCLK12 IO_L04N_2/D3/GCLK15 IO_L04P_2/D4/GCLK14 IO_L06N_2/D1/GCLK3 IO_L06P_2/D2/GCLK2 IO_L07N_2/DIN/D0 IO_L07P_2/M0 IO_L08N_2/VS1 IO_L08P_2/VS2 VQ100 Pin Number P97 P54 P53 P58 P57 P61 P60 P63 P62 P66 P65 P68 P67 P71 P70 P69 P55 P73 P34 P42 P25 P24 P27 P26 P33 P32 P36 P35 P41 P40 P44 P43 P48 P47
Bank 0 1 1 1 1 1 1 1 1 1 1
Type VCCO I/O I/O I/O I/O RHCLK RHCLK RHCLK RHCLK RHCLK RHCLK RHCLK RHCLK I/O I/O VREF VCCO VCCO DUAL DUAL DUAL DUAL DUAL DUAL DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL DUAL DUAL DUAL
Pinout Table
Table 7 shows the pinout for production Spartan-3E FPGAs in the VQ100 package. The XC3S100 engineering samples have a slightly different pinout, as described in Table 9.
1 1 1 1 VQ100 Pin Number P92 P79 P78 P84 P83 P86 P85 P91 P90 P95 P94 P99 P98 P89 P88 P82 1 Type I/O I/O I/O GCLK GCLK GCLK GCLK GCLK GCLK VREF I/O DUAL I/O GCLK GCLK VCCO 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Table 7: VQ100 Package Pinout
XC3S100E XC3S250E Pin Name IO IO_L01N_0 IO_L01P_0 IO_L02N_0/GCLK5 IO_L02P_0/GCLK4 IO_L03N_0/GCLK7 IO_L03P_0/GCLK6 IO_L05N_0/GCLK11 IO_L05P_0/GCLK10 IO_L06N_0/VREF_0 IO_L06P_0 IO_L07N_0/HSWAP IO_L07P_0 IP_L04N_0/GCLK9 IP_L04P_0/GCLK8 VCCO_0
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Table 7: VQ100 Package Pinout
XC3S100E XC3S250E Pin Name IO_L09N_2/CCLK IO_L09P_2/VS0 IP/VREF_2 IP_L05N_2/M2/GCLK1 IP_L05P_2/RDWR_B/ GCLK0 VCCO_2 VCCO_2 IO_L01N_3 IO_L01P_3 IO_L02N_3/VREF_3 IO_L02P_3 IO_L03N_3/LHCLK1 IO_L03P_3/LHCLK0 IO_L04N_3/LHCLK3 IO_L04P_3/LHCLK2 IO_L05N_3/LHCLK5 IO_L05P_3/LHCLK4 IO_L06N_3/LHCLK7 IO_L06P_3/LHCLK6 IO_L07N_3 IO_L07P_3 IP VCCO_3 VCCO_3 GND GND GND GND GND GND GND GND GND GND VQ100 Pin Number P50 P49 P30 P39 P38 P31 P45 P3 P2 P5 P4 P10 P9 P12 P11 P16 P15 P18 P17 P23 P22 P13 P8 P20 P7 P14 P19 P29 P37 P52 P59 P64 P72 P81
Table 7: VQ100 Package Pinout
XC3S100E XC3S250E Pin Name GND GND VQ100 Pin Number P87 P93 P51 P1 P77 P100 P76 P75 P21 P46 P74 P96 P6 P28 P56 P80
Bank 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 GND GND GND GND GND GND GND GND GND GND
Type DUAL DUAL VREF DUAL/GCLK DUAL/GCLK VCCO VCCO I/O I/O VREF I/O LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK I/O I/O INPUT VCCO VCCO GND GND GND GND GND GND GND GND GND GND
Bank GND GND
Type GND GND CONFIG CONFIG JTAG JTAG JTAG JTAG VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT
VCCAUX DONE VCCAUX PROG_B VCCAUX TCK VCCAUX TDI VCCAUX TDO VCCAUX TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
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User I/Os by Bank
Table 8 indicates how the 66 available user-I/O pins are distributed between the four I/O banks on the VQ100 package.
Table 8: User I/Os Per Bank for XC3S100E and XC3S250E in the VQ100 Package
Package Edge Top Right Bottom Left TOTAL Maximum I/O 15 15 19 17 66 All Possible I/O Pins by Type I/O 5 6 0 5 16 INPUT 0 0 0 1 1 DUAL 1 0 18 2 21 VREF 1 1 1 1 4 GCLK 8 8 0 8 24
I/O Bank 0 1 2 3
Footprint Migration Differences
The production XC3S100E and XC3S250E FPGAs have identical footprints in the VQ100 package. Designs can migrate between the XC3S100E and XC3S250E without further consideration. The pinout changed slightly between the XC3S100E engineering samples and the production devices, as shown in Table 9. In the engineering samples, the mode select pins M1 and M0 overlap with two global clock inputs feeding the bottom-edge global buffers and DCMs. In the production devices, the mode pins are swapped with parallel mode data pins, D1 and D2. This way, these two mode pins do not interfere with global clock inputs.
Table 9: XC3S100E Pinout Changes between Production Devices and Engineering Samples
XC3S100E Production Devices D2/GCLK2 D1/GCLK3 M1 M0 XC3S100E Engineering Samples M1/GCLK2 M0/GCLK3 D2 D1
VQ100 Pin P40 P41 P42 P43
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VQ100 Footprint
In Figure 2, note pin 1 indicator in top-left corner and logo orientation. The engineering sample footprint is slightly different.
TDI IO_L07N_0/HSWAP IO_L07P_0 VCCO_0 VCCAUX IO_L06N_0/VREF_0 IO_L06P_0 GND IO IO_L05N_0/GCLK11 IO_L05P_0/GCLK10 IP_L04N_0/GCLK9 IP_L04P_0/GCLK8 GND IO_L03N_0/GCLK7 IO_L03P_0/GCLK6 IO_L02N_0/GCLK5 IO_L02P_0/GCLK4 VCCO_0 GND VCCINT IO_L01N_0 IO_L01P_0 TCK TDO PROG_B IO_L01P_3 IO_L01N_3 IO_L02P_3 IO_L02N_3/VREF_3 VCCINT GND VCCO_3 IO_L03P_3/LHCLK0 IO_L03N_3/LHCLK1 IO_L04P_3/LHCLK2 IO_L04N_3/LHCLK3 IP GND IO_L05P_3/LHCLK4 IO_L05N_3/LHCLK5 IO_L06P_3/LHCLK6 IO_L06N_3/LHCLK7 GND VCCO_3 VCCAUX IO_L07P_3 IO_L07N_3 IO_L01P_2/CSO_B IO_L01N_2/INIT_B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
Bank 0
TMS VCCAUX VCCO_1 GND IO_L07N_1 IO_L07P_1 IP/VREF_1 IO_L06N_1/RHCLK7 IO_L06P_1/RHCLK6 IO_L05N_1/RHCLK5 IO_L05P_1/RHCLK4 GND IO_L04N_1/RHCLK3 IO_L04P_1/RHCLK2 IO_L03N_1/RHCLK1 IO_L03P_1/RHCLK0 GND IO_L02N_1 IO_L02P_1 VCCINT VCCO_1 IO_L01N_1 IO_L01P_1 GND DONE
Bank 3
Bank 2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 IO_L02P_2/DOUT/BUSY IO_L02N_2/MOSI/CSI_B VCCINT GND IP/VREF_2 VCCO_2 IO_L03P_2/D7/GCLK12 IO_L03N_2/D6/GCLK13 IO/D5 IO_L04P_2/D4/GCLK14 IO_L04N_2/D3/GCLK15 GND IP_L05P_2/RDWR_B/GCLK0 IP_L05N_2/M2/GCLK1 IO_L06P_2/D2/GCLK2 IO_L06N_2/D1/GCLK3 IO/M1 IO_L07P_2/M0 IO_L07N_2/DIN/D0 VCCO_2 VCCAUX IO_L08P_2/VS2 IO_L08N_2/VS1 IO_L09P_2/VS0 IO_L09N_2/CCLK
Bank 1
DS312-4_02_030705
Figure 2: VQ100 Package Production Footprint (top view). Engineering Samples have slightly different footprint.
16 1 2 0
I/O: Unrestricted, general-purpose user I/O INPUT: Unrestricted, general-purpose input pin CONFIG: Dedicated configuration pins N.C.: Not connected
21 24 4 12
DUAL: Configuration pin, then possible user-I/O GCLK: User I/O, input, or global buffer input JTAG: Dedicated JTAG port pins GND: Ground
4 8 4 4
VREF: User I/O or input voltage reference for bank VCCO: Output voltage supply for bank VCCINT: Internal core supply voltage (+1.2V) VCCAUX: Auxiliary supply voltage (+2.5V)
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CP132: 132-ball Chip-scale Package
The XC3S250E and the XC3S500E FPGAs are available in the 132-lead chip-scale package, CP132. Both devices share a common footprint for this package as shown in Table 10 and Figure 3. Table 10 lists all the CP132 package pins. They are sorted by bank number and then by pin name. Pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier. Physically, the D14 and K2 balls on the XC3S250E FPGA are not connected but should be connected to VCCINT to maintain density migration compatibility. An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Table 10: CP132 Package Pinout
XC3S250E XC3S500E Pin Name IP_L06N_0/GCLK9 IP_L06P_0/GCLK8 VCCO_0 VCCO_0 IO/A0 IO/VREF_1 IO_L01N_1/A15 IO_L01P_1/A16 IO_L02N_1/A13 IO_L02P_1/A14 IO_L03N_1/A11 IO_L03P_1/A12 IO_L04N_1/A9/RHCLK1 IO_L04P_1/A10/RHCLK0 IO_L05N_1/A7/RHCLK3/ TRDY1 IO_L05P_1/A8/RHCLK2 IO_L06N_1/A5/RHCLK5 IO_L06P_1/A6/RHCLK4/ IRDY1 IO_L07N_1/A3/RHCLK7 IO_L07P_1/A4/RHCLK6 IO_L08N_1/A1 IO_L08P_1/A2 IO_L09N_1/LDC0 IO_L09P_1/HDC IO_L10N_1/LDC2 IO_L10P_1/LDC1 IP/VREF_1 VCCO_1 VCCO_1 IO/D5 CP132 Ball C8 B8 A6 B10 F12 K13 N14 N13 M13 M12 L14 L13 J12 K14 J14 J13 H12 H13 G13 G14 F13 F14 D12 D13 C13 C14 G12 E13 M14 P4
Bank 0 0 0 0 1 1 1 1 1 1 1
Type GCLK GCLK VCCO VCCO DUAL VREF DUAL DUAL DUAL DUAL DUAL DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL DUAL DUAL DUAL DUAL DUAL DUAL VREF VCCO VCCO DUAL
Pinout Table
Table 10: CP132 Package Pinout
XC3S250E XC3S500E Pin Name IO_L01N_0 IO_L01P_0 IO_L02N_0 IO_L02P_0 IO_L03N_0/VREF_0 IO_L03P_0 IO_L04N_0/GCLK5 IO_L04P_0/GCLK4 IO_L05N_0/GCLK7 IO_L05P_0/GCLK6 IO_L07N_0/GCLK11 IO_L07P_0/GCLK10 IO_L08N_0/VREF_0 IO_L08P_0 IO_L09N_0 IO_L09P_0 IO_L10N_0 IO_L10P_0 IO_L11N_0/HSWAP IO_L11P_0 CP132 Ball C12 A13 A12 B12 B11 C11 C9 A10 A9 B9 B7 A7 C6 B6 C5 B5 C4 B4 B3 A3
1 1 Type I/O I/O I/O I/O VREF I/O GCLK GCLK GCLK GCLK GCLK GCLK VREF I/O I/O I/O I/O I/O DUAL I/O 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Table 10: CP132 Package Pinout
XC3S250E XC3S500E Pin Name IO/M1 IO/VREF_2 IO_L01N_2/INIT_B IO_L01P_2/CSO_B IO_L02N_2/MOSI/CSI_B IO_L02P_2/DOUT/BUSY IO_L03N_2/D6/GCLK13 IO_L03P_2/D7/GCLK12 IO_L04N_2/D3/GCLK15 IO_L04P_2/D4/GCLK14 IO_L06N_2/D1/GCLK3 IO_L06P_2/D2/GCLK2 IO_L07N_2/DIN/D0 IO_L07P_2/M0 IO_L08N_2/A22 IO_L08P_2/A23 IO_L09N_2/A20 IO_L09P_2/A21 IO_L10N_2/VS1/A18 IO_L10P_2/VS2/A19 IO_L11N_2/CCLK IO_L11P_2/VS0/A17 IP/VREF_2 IP_L05N_2/M2/GCLK1 IP_L05P_2/RDWR_B/ GCLK0 VCCO_2 VCCO_2 IO IO/VREF_3 IO_L01N_3 CP132 Ball N7 P11 N1 M2 N2 P1 N4 M4 N5 M5 P7 P6 N8 P8 M9 N9 M10 N10 M11 N11 N12 P12 N3 N6 M6 M8 P3 J3 K3 B1
Table 10: CP132 Package Pinout
XC3S250E XC3S500E Pin Name IO_L01P_3 IO_L02N_3 IO_L02P_3 IO_L03N_3 IO_L03P_3 IO_L04N_3/LHCLK1 IO_L04P_3/LHCLK0 IO_L05N_3/LHCLK3/IRDY2 IO_L05P_3/LHCLK2 IO_L06N_3/LHCLK5 IO_L06P_3/LHCLK4/TRDY2 IO_L07N_3/LHCLK7 IO_L07P_3/LHCLK6 IO_L08N_3 IO_L08P_3 IO_L09N_3 IO_L09P_3 IP/VREF_3 VCCO_3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND CP132 Ball B2 C2 C3 D1 D2 F2 F3 G1 F1 H1 G3 H3 H2 L2 L1 M1 L3 E2 E1 J2 A4 A8 C1 C7 C10 E3 E14 G2 H14 J1 K12 M3 M7 P5
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3
Type DUAL VREF DUAL DUAL DUAL DUAL DUAL/ GCLK DUAL/ GCLK DUAL/ GCLK DUAL/ GCLK DUAL/ GCLK DUAL/ GCLK DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL VREF DUAL/ GCLK DUAL/ GCLK VCCO VCCO I/O VREF I/O
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Type I/O I/O I/O I/O I/O LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK I/O I/O I/O I/O VREF VCCO VCCO GND GND GND GND GND GND GND GND GND GND GND GND GND GND
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Table 10: CP132 Package Pinout
XC3S250E XC3S500E Pin Name GND GND CP132 Ball P10 P14 P13 A1 B13 A2 A14 B14 A5 E12 K1
Table 10: CP132 Package Pinout
XC3S250E XC3S500E Pin Name CP132 Ball P9 A11 D3 D14 K2 L12 P2
Bank GND GND
Type GND GND CONFIG CONFIG JTAG JTAG JTAG JTAG VCCAUX VCCAUX VCCAUX
Bank
Type VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
VCCAUX DONE VCCAUX PROG_B VCCAUX TCK VCCAUX TDI VCCAUX TDO VCCAUX TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX
User I/Os by Bank
Table 20 indicates how the 92 available user-I/O pins are distributed between the four I/O banks on the CP132 package.
Table 11: User I/Os Per Bank for the XC3S250E and XC3S500E in the CP132 Package
Package Edge Top Right Bottom Left TOTAL Maximum I/O 22 23 26 21 92 All Possible I/O Pins by Type I/O 11 0 0 11 22 INPUT 0 0 0 0 0 DUAL 1 21 24 0 46 VREF 2 2 2 2 8 GCLK 8 0 0 8 16
I/O Bank 0 1 2 3
Footprint Migration Differences
The production XC3S250E and XC3S500E FPGAs have identical footprints in the CP132 package. Designs can
migrate between the XC3S250E and XC3S500E without further consideration.
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CP132 Footprint
Bank 0
1 A
PROG_B
2
TDI
3
I/O
L11P_0
4
GND
5
VCCAUX
6
VCCO_0
7
I/O
L07P_0 GCLK10
8
GND INPUT
L06P_0 GCLK8
9
I/O
L05N_0 GCLK7
10
I/O
L04P_0 GCLK4
11
VCCINT
12
I/O
L02N_0
13
I/O
L01P_0
14
TDO
B
I/O
L01N_3
I/O
L01P_3
I/O
L11N_0 HSWAP
I/O
L10P_0
I/O
L09P_0
I/O
L08P_0
I/O
L07N_0 GCLK11
I/O
L05P_0 GCLK6
VCCO_0
I/O
L03N_0 VREF_0
I/O
L02P_0
TCK
TMS
C
GND
I/O
L02N_3
I/O
L02P_3
I/O
L10N_0
I/O
L09N_0
I/O
L08N_0 VREF_0
INPUT GND
L06N_0 GCLK9
I/O
L04N_0 GCLK5
GND
I/O
L03P_0
I/O
L01N_0
I/O
L10N_1 LDC2
I/O
L10P_1 LDC1
D
I/O
L03N_3
I/O
L03P_3
I/O
VCCINT
L09N_1 LDC0
I/O
L09P_1 HDC
VCCINT
E
VCCO_3
INPUT
VREF_3
GND
VCCAUX
VCCO_1
GND
I/O
I/O
L04N_3 LHCLK1
I/O
L04P_3 LHCLK0
F
Bank 3
L05P_3 LHCLK2
I/O
A0
I/O
L08N_1 A1
I/O
L08P_1 A2
I/O
I/O
GND
L06P_3 LHCLK4 TRDY2
G
L05N_3 LHCLK3 IRDY2
INPUT
VREF_1
I/O
L07N_1 A3 RHCLK7 L06P_1 A6 RHCLK4 IRDY1
I/O
L07P_1 A4 RHCLK6
I/O
I/O
L07P_3 LHCLK6
I/O
L07N_3 LHCLK7
I/O
L06N_1 A5 RHCLK5
I/O
H
L06N_3 LHCLK5
GND
I/O
I/O
L05P_1 A8 RHCLK2
J
GND
VCCO_3
I/O
L04N_1 A9 RHCLK1
L05N_1 A7 RHCLK3 TRDY1
I/O
K
VCCAUX
VCCINT
I/O
VREF_3
GND
I/O
VREF_1
I/O
L04P_1 A10 RHCLK0
L
I/O
L08P_3
I/O
L08N_3
I/O
L09P_3
I/O
VCCINT
L03P_1 A12
I/O
L03N_1 A11
M
I/O
L09N_3
I/O
L01P_2 CSO_B
I/O
GND
L03P_2 D7 GCLK12
I/O
L04P_2 D4 GCLK14
INPUT
L05P_2 RDWR_B GCLK0
I/O
GND
VCCO_2
I/O
L09N_2 A20
I/O
L10N_2 VS1 A18
I/O
L02P_1 A14
I/O
L02N_1 A13
VCCO_1
L08N_2 A22
I/O
I/O
L02N_2 MOSI CSI_B
N
L01N_2 INIT_B
INPUT
VREF_2
I/O
L03N_2 D6 GCLK13
I/O
L04N_2 D3 GCLK15
INPUT
L05N_2 M2 GCLK1
I/O
M1
I/O
L07N_2 DIN D0
I/O
L08P_2 A23
I/O
L09P_2 A21
I/O
L10P_2 VS2 A19
I/O
L11N_2 CCLK
I/O
L01P_1 A16
I/O
L01N_1 A15
I/O
P
L02P_2 DOUT BUSY
VCCINT VCCO_2
I/O
D5
I/O
GND
L06P_2 D2 GCLK2
I/O
L06N_2 D1 GCLK3
I/O
L07P_2 M0
VCCAUX
GND
I/O
VREF_2
I/O
L11P_2 VS0 A17
DONE
GND
Bank 2
DS312-4_07_031105
Figure 3: CP132 Package Footprint (top view)
22 0 2 0
I/O: Unrestricted, general-purpose user I/O INPUT: Unrestricted, general-purpose input pin CONFIG: Dedicated configuration pins N.C.: Not connected
42 16 4 16
DUAL: Configuration pin, then possible user I/O GCLK: User I/O, input, or global buffer input JTAG: Dedicated JTAG port pins GND: Ground
8 8 6 4
VREF: User I/O or input voltage reference for bank VCCO: Output voltage supply for bank VCCINT: Internal core supply voltage (+1.2V) VCCAUX: Auxiliary supply voltage (+2.5V)
DS312-4 (v1.1) March 21, 2005 Advance Product Specification
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Bank 1
13
Pinout Descriptions
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TQ144: 144-lead Thin Quad Flat Package
The XC3S100E and the XC3S250E FPGAs are available in the 144-lead thin quad flat package, TQ144. Both devices share a common footprint for this package as shown in Table 12 and Figure 4. Table 12 lists all the package pins. They are sorted by bank number and then by pin name of the largest device. Pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier. The TQ144 package only supports 20 address output pins in the Byte-wide Peripheral Interface (BPI) configuration
mode. In larger packages, there are 24 BPI address outputs. An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx web site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Pinout Table
Table 12 shows the pinout for production Spartan-3E FPGAs in the VQ100 package. The XC3S100 engineering samples have a slightly different pinout, as described in Table 15.
Table 12: TQ144 Package Pinout
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO IO/VREF_0 IO_L01N_0 IO_L01P_0 IO_L02N_0 IO_L02P_0 IO_L04N_0/GCLK5 IO_L04P_0/GCLK4 IO_L05N_0/GCLK7 IO_L05P_0/GCLK6 IO_L07N_0/GCLK11 IO_L07P_0/GCLK10 IO_L08N_0/VREF_0 IO_L08P_0 IO_L09N_0 IO_L09P_0 IO_L10N_0/HSWAP IO_L10P_0 IP IP IP IP IP_L03N_0 IP_L03P_0 IP_L06N_0/GCLK9 IP_L06P_0/GCLK8 XC3S100E Pin Name IO IO/VREF_0 IO_L01N_0 IO_L01P_0 IO_L02N_0 IO_L02P_0 IO_L04N_0/GCLK5 IO_L04P_0/GCLK4 IO_L05N_0/GCLK7 IO_L05P_0/GCLK6 IO_L07N_0/GCLK11 IO_L07P_0/GCLK10 IO_L08N_0/VREF_0 IO_L08P_0 IO_L09N_0 IO_L09P_0 IO_L10N_0/HSWAP IO_L10P_0 IP IP IP IP IP_L03N_0 IP_L03P_0 IP_L06N_0/GCLK9 IP_L06P_0/GCLK8 XC3S250E Pin Name TQ144 Pin P132 P124 P113 P112 P117 P116 P123 P122 P126 P125 P131 P130 P135 P134 P140 P139 P143 P142 P111 P114 P136 P141 P120 P119 P129 P128 Type I/O VREF I/O I/O I/O I/O GCLK GCLK GCLK GCLK GCLK GCLK VREF I/O I/O I/O DUAL I/O INPUT INPUT INPUT INPUT INPUT INPUT GCLK GCLK
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Pinout Descriptions
Table 12: TQ144 Package Pinout (Continued)
Bank 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 XC3S100E Pin Name VCCO_0 VCCO_0 IO/A0 IO/VREF_1 IO_L01N_1/A15 IO_L01P_1/A16 IO_L02N_1/A13 IO_L02P_1/A14 IO_L03N_1/A11 IO_L03P_1/A12 IO_L04N_1/A9/RHCLK1 IO_L04P_1/A10/RHCLK0 IO_L05N_1/A7/RHCLK3/TRDY1 IO_L05P_1/A8/RHCLK2 IO_L06N_1/A5/RHCLK5 IO_L06P_1/A6/RHCLK4/IRDY1 IO_L07N_1/A3/RHCLK7 IO_L07P_1/A4/RHCLK6 IO_L08N_1/A1 IO_L08P_1/A2 IO_L09N_1/LDC0 IO_L09P_1/HDC IO_L10N_1/LDC2 IO_L10P_1/LDC1 IP IP IP IP IP IP/VREF_1 VCCO_1 VCCO_1 IO/D5 IO/M1 IP/VREF_2 XC3S250E Pin Name VCCO_0 VCCO_0 IO/A0 IO/VREF_1 IO_L01N_1/A15 IO_L01P_1/A16 IO_L02N_1/A13 IO_L02P_1/A14 IO_L03N_1/A11 IO_L03P_1/A12 IO_L04N_1/A9/RHCLK1 IO_L04P_1/A10/RHCLK0 IO_L05N_1/A7/RHCLK3 IO_L05P_1/A8/RHCLK2 IO_L06N_1/A5/RHCLK5 IO_L06P_1/A6/RHCLK4 IO_L07N_1/A3/RHCLK7 IO_L07P_1/A4/RHCLK6 IO_L08N_1/A1 IO_L08P_1/A2 IO_L09N_1/LDC0 IO_L09P_1/HDC IO_L10N_1/LDC2 IO_L10P_1/LDC1 IP IP IP IP IP IP/VREF_1 VCCO_1 VCCO_1 IO/D5 IO/M1 IO/VREF_2 TQ144 Pin P121 P138 P98 P83 P75 P74 P77 P76 P82 P81 P86 P85 P88 P87 P92 P91 P94 P93 P97 P96 P104 P103 P106 P105 P78 P84 P89 P101 P107 P95 P79 P100 P52 P60 P66 Type VCCO VCCO DUAL VREF DUAL DUAL DUAL DUAL DUAL DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL DUAL DUAL DUAL DUAL DUAL DUAL INPUT INPUT INPUT INPUT INPUT VREF VCCO VCCO DUAL DUAL
100E: VREF(INPUT) 250E: VREF(I/O)
DS312-4 (v1.1) March 21, 2005 Advance Product Specification
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15
Pinout Descriptions
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Table 12: TQ144 Package Pinout (Continued)
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 XC3S100E Pin Name IO_L01N_2/INIT_B IO_L01P_2/CSO_B IO_L02N_2/MOSI/CSI_B IO_L02P_2/DOUT/BUSY IO_L04N_2/D6/GCLK13 IO_L04P_2/D7/GCLK12 IO_L05N_2/D3/GCLK15 IO_L05P_2/D4/GCLK14 IO_L07N_2/D1/GCLK3 IO_L07P_2/D2/GCLK2 IO_L08N_2/DIN/D0 IO_L08P_2/M0 IO_L09N_2/VS1/A18 IO_L09P_2/VS2/A19 IO_L10N_2/CCLK IO_L10P_2/VS0/A17 IP IP IP IP_L03N_2/VREF_2 IP_L03P_2 IP_L06N_2/M2/GCLK1 IP_L06P_2/RDWR_B/GCLK0 VCCO_2 VCCO_2 VCCO_2 IP/VREF_3 XC3S250E Pin Name IO_L01N_2/INIT_B IO_L01P_2/CSO_B IO_L02N_2/MOSI/CSI_B IO_L02P_2/DOUT/BUSY IO_L04N_2/D6/GCLK13 IO_L04P_2/D7/GCLK12 IO_L05N_2/D3/GCLK15 IO_L05P_2/D4/GCLK14 IO_L07N_2/D1/GCLK3 IO_L07P_2/D2/GCLK2 IO_L08N_2/DIN/D0 IO_L08P_2/M0 IO_L09N_2/VS1/A18 IO_L09P_2/VS2/A19 IO_L10N_2/CCLK IO_L10P_2/VS0/A17 IP IP IP IP_L03N_2/VREF_2 IP_L03P_2 IP_L06N_2/M2/GCLK1 IP_L06P_2/RDWR_B/GCLK0 VCCO_2 VCCO_2 VCCO_2 IO/VREF_3 TQ144 Pin P40 P39 P44 P43 P51 P50 P54 P53 P59 P58 P63 P62 P68 P67 P71 P70 P38 P41 P69 P48 P47 P57 P56 P42 P49 P64 P31 Type DUAL DUAL DUAL DUAL DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL DUAL DUAL DUAL DUAL DUAL INPUT INPUT INPUT VREF INPUT DUAL/GCLK DUAL/GCLK VCCO VCCO VCCO
100E: VREF(INPUT) 250E: VREF(I/O)
3 3 3 3 3 3 3 3
IO_L01N_3 IO_L01P_3 IO_L02N_3/VREF_3 IO_L02P_3 IO_L03N_3 IO_L03P_3 IO_L04N_3/LHCLK1 IO_L04P_3/LHCLK0
IO_L01N_3 IO_L01P_3 IO_L02N_3/VREF_3 IO_L02P_3 IO_L03N_3 IO_L03P_3 IO_L04N_3/LHCLK1 IO_L04P_3/LHCLK0
P3 P2 P5 P4 P8 P7 P15 P14
I/O I/O VREF I/O I/O I/O LHCLK LHCLK
16
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DS312-4 (v1.1) March 21, 2005 Advance Product Specification
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Pinout Descriptions
Table 12: TQ144 Package Pinout (Continued)
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 XC3S100E Pin Name IO_L05N_3/LHCLK3/IRDY2 IO_L05P_3/LHCLK2 IO_L06N_3/LHCLK5 IO_L06P_3/LHCLK4/TRDY2 IO_L07N_3/LHCLK7 IO_L07P_3/LHCLK6 IO_L08N_3 IO_L08P_3 IO_L09N_3 IO_L09P_3 IO_L10N_3 IO_L10P_3 IP IO XC3S250E Pin Name IO_L05N_3/LHCLK3 IO_L05P_3/LHCLK2 IO_L06N_3/LHCLK5 IO_L06P_3/LHCLK4 IO_L07N_3/LHCLK7 IO_L07P_3/LHCLK6 IO_L08N_3 IO_L08P_3 IO_L09N_3 IO_L09P_3 IO_L10N_3 IO_L10P_3 IP IP TQ144 Pin P17 P16 P21 P20 P23 P22 P26 P25 P33 P32 P35 P34 P6 P10 Type LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK I/O I/O I/O I/O I/O I/O INPUT
100E: I/O 250E: INPUT
3 3 3
IP IP IO
IP IP IP
P18 P24 P29
INPUT INPUT
100E: I/O 250E: INPUT
3 3 3 3 GND GND GND GND GND GND GND GND GND GND GND GND GND
IP IP/VREF_3 VCCO_3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND
IP IP/VREF_3 VCCO_3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND
P36 P12 P13 P28 P11 P19 P27 P37 P46 P55 P61 P73 P90 P99 P118 P127 P133
INPUT VREF VCCO VCCO GND GND GND GND GND GND GND GND GND GND GND GND GND
DS312-4 (v1.1) March 21, 2005 Advance Product Specification
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Pinout Descriptions
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Table 12: TQ144 Package Pinout (Continued)
Bank VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT DONE PROG_B TCK TDI TDO TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT XC3S100E Pin Name DONE PROG_B TCK TDI TDO TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT XC3S250E Pin Name TQ144 Pin P72 P1 P110 P144 P109 P108 P30 P65 P102 P137 P9 P45 P80 P115 Type CONFIG CONFIG JTAG JTAG JTAG JTAG VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT
User I/Os by Bank
Table 13 and Table 14 indicate how the 108 available user-I/O pins are distributed between the four I/O banks on the TQ144 package.
Table 13: User I/Os Per Bank for the XC3S100E in the TQ144 Package
Package Edge Top Right Bottom Left TOTAL Maximum I/O 26 28 26 28 108 All Possible I/O Pins by Type I/O 9 0 0 13 22 INPUT 6 5 4 4 19 DUAL 1 21 20 0 42 VREF 2 2 2 3 9 GCLK 8 0 0 8 16
I/O Bank 0 1 2 3
Table 14: User I/Os Per Bank for the XC3S250E in TQ144 Package
Package Edge Top Right Bottom Left TOTAL Maximum I/O 26 28 26 28 108 All Possible I/O Pins by Type I/O 9 0 0 11 20 INPUT 6 5 4 6 21 DUAL 1 21 20 0 42 VREF 2 2 2 3 9 GCLK 8 0 0 8 16
I/O Bank 0 1 2 3
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DS312-4 (v1.1) March 21, 2005 Advance Product Specification
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Pinout Descriptions The arrows indicate the direction for easy migration. For example, a left-facing arrow indicates that the pin on the XC3S250E unconditionally migrates to the pin on the XC3S100E. It may be possible to migrate the opposite direction depending on the I/O configuration. For example, an I/O pin (Type = I/O) can migrate to an input-only pin (Type = INPUT) if the I/O pin is configured as an input.
Footprint Migration Differences
Table 15 summarizes any footprint and functionality differences between the XC3S100E and the XC3S250E FPGAs that may affect easy migration between devices. There are four such pins. All other pins not listed in Table 15 unconditionally migrate between Spartan-3E devices available in the TQ144 package.
Table 15: TQ144 Footprint Migration Differences
TQ144 Pin P10 P29 P31 P66 Bank 3 3 3 2 I/O I/O VREF(INPUT) VREF(INPUT) 4 XC3S100E Type Migration XC3S250E Type INPUT INPUT VREF(I/O) VREF(I/O)
DIFFERENCES
Legend:
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be possible depending on how the pin is configured for the device on the right. This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be possible depending on how the pin is configured for the device on the left.
The pinout changed slightly between the XC3S100E engineering samples and the production devices, as shown in Table 16. In the engineering samples, the mode select pins M1 and M0 overlap with two global clock inputs feeding the bottom edge global buffers and DCMs. In the production devices, the mode pins are swapped with parallel mode data pins, D1 and D2. This way, these two mode pins do not interfere with global clock inputs.
Table 16: XC3S100E Pinout Changes between Production Devices and Engineering Samples
XC3S100E Production Devices D2/GCLK2 D1/GCLK3 M1 M0 XC3S100E Engineering Samples M1/GCLK2 M0/GCLK3 D2 D1
TQ144 Pin P58 P59 P60 P62
DS312-4 (v1.1) March 21, 2005 Advance Product Specification
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Pinout Descriptions
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TQ144 Footprint
Note pin 1 indicator in top-left corner and logo orientation. Double arrows ( ) indicates a pinout migration difference
132 IO 131 IO_L07N_0/GCLK11 136 IP 135 IO_L08N_0/VREF_0 130 IO_L07P_0/GCLK10 129 IP_L06N_0/GCLK9 144 TDI 143 IO_L10N_0/HSWAP 128 IP_L06P_0/GCLK8 127 GND
between the XC3S100E and XC3S250E. Engineering sample footprint is slightly different.
126 IO_L05N_0/GCLK7 125 IO_L05P_0/GCLK6
124 IO/VREF_0 123 IO_L04N_0/GCLK5
122 IO_L04P_0/GCLK4 121 VCCO_0
140 IO_L09N_0 139 IO_L09P_0
118 GND 117 IO_L02N_0
114 IP 113 IO_L01N_0
142 IO_L10P_0 141 IP
134 IO_L08P_0 133 GND
116 IO_L02P_0 115 VCCINT
112 IO_L01P_0 111 IP
120 IP_L03N_0 119 IP_L03P_0
138 VCCO_0 137 VCCAUX
PROG_B IO_L01P_3 IO_L01N_3 IO_L02P_3 IO_L02N_3/VREF_3 IP IO_L03P_3 IO_L03N_3 VCCINT ( ) IP
1 2
110 TCK 109 TDO 108 TMS 107 IP 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 IO_L10N_1/LDC2 IO_L10P_1/LDC1 IO_L09N_1/LDC0 IO_L09P_1/HDC VCCAUX IP VCCO_1 GND IO/A0 IO_L08N_1/A1 IO_L08P_1/A2 IP/VREF_1 IO_L07N_1/A3/RHCLK7 IO_L07P_1/A4/RHCLK6 IO_L06N_1/A5/RHCLK5 IO_L06P_1/A6/RHCLK4 GND IP IO_L05N_1/A7/RHCLK3 IO_L05P_1/A8/RHCLK2 IO_L04N_1/A9/RHCLK1 IO_L04P_1/A10/RHCLK0 IP IO/VREF_1 IO_L03N_1/A11 IO_L03P_1/A12 VCCINT VCCO_1 IP IO_L02N_1/A13 IO_L02P_1/A14 IO_L01N_1/A15 IO_L01P_1/A16 GND IO_L10N_2/CCLK DONE 71 72
Bank 0
3 4 5 6 7 8 9 10 GND 11 IP/VREF_3 12 VCCO_3 13 IO_L04P_3/LHCLK0 14 IO_L04N_3/LHCLK1 15 IO_L05P_3/LHCLK2 16 IO_L05N_3/LHCLK3 17 IP 18 GND 19 IO_L06P_3/LHCLK4 20 IO_L06N_3/LHCLK5 21 IO_L07P_3/LHCLK6 22 IO_L07N_3/LHCLK7 23 IP 24 IO_L08P_3 25 IO_L08N_3 26 GND 27 VCCO_3 28 ( ) IP 29 VCCAUX 30 ( ) IO/VREF_3 31 IO_L09P_3 32 IO_L09N_3 33 IO_L10P_3 34 IO_L10N_3 35 IP 36
Bank 3
Bank 2
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 IP IO_L10P_2/VS0/A17
GND IP
VCCINT GND
GND IP_L06P_2/RDWR_B/GCLK0
IP_L03P_2 IP_L03N_2/VREF_2
GND IO_L08P_2/M0
IO_L04N_2/D6/GCLK13 IO/D5
IP_L06N_2/M2/GCLK1 IO_L07P_2/D2/GCLK2
IO_L07N_2/D1/GCLK3 IO/M1
IO_L02P_2/DOUT/BUSY IO_L02N_2/MOSI/CSI_B
VCCO_2 IO_L04P_2/D7/GCLK12
IO_L05P_2/D4/GCLK14 IO_L05N_2/D3/GCLK15
IO_L09P_2/VS2/A19 IO_L09N_2/VS1/A18
IO_L01P_2/CSO_B IO_L01N_2/INIT_B
IO_L08N_2/DIN/D0 VCCO_2
(
VCCAUX ) IO/VREF_2
IP VCCO_2
Bank 1
DS312-4_01_030705
Figure 4: TQ144 Package Production Footprint (top view)
20 21 2 0
20
I/O: Unrestricted, general-purpose user I/O INPUT: Unrestricted, general-purpose input pin CONFIG: Dedicated configuration pins N.C.: Not connected
42 16 4 13
DUAL: Configuration pin, then possible user I/O GCLK: User I/O, input, or global buffer input JTAG: Dedicated JTAG port pins GND: Ground
9 9 4 4
VREF: User I/O or input voltage reference for bank VCCO: Output voltage supply for bank VCCINT: Internal core supply voltage (+1.2V) VCCAUX: Auxiliary supply voltage (+2.5V)
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Pinout Descriptions
PQ208: 208-pin Plastic Quad Flat Package
The 208-pin plastic quad flat package, PQ208, supports two different Spartan-3E FPGAs, including the XC3S250E and the XC3S500E. Table 17 lists all the PQ208 package pins. They are sorted by bank number and then by pin name. Pairs of pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier. An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Table 17: PQ208 Package Pinout
XC3S250E XC3S500E Pin Name IO_L13P_0 IO_L14N_0/VREF_0 IO_L14P_0 IO_L15N_0 IO_L15P_0 IO_L16N_0/HSWAP IO_L16P_0 IP IP IP IP IP_L06N_0 IP_L06P_0 IP_L09N_0/GCLK9 IP_L09P_0/GCLK8 VCCO_0 VCCO_0 VCCO_0 IO_L01N_1/A15 IO_L01P_1/A16 IO_L02N_1/A13 IO_L02P_1/A14 IO_L03N_1/VREF_1 IO_L03P_1 IO_L04N_1 IO_L04P_1 IO_L05N_1/A11 IO_L05P_1/A12 IO_L06N_1/VREF_1 IO_L06P_1 IO_L07N_1/A9/RHCLK1 IO_L07P_1/A10/RHCLK0 IO_L08N_1/A7/RHCLK3 IO_L08P_1/A8/RHCLK2 PQ208 Pin P196 P200 P199 P203 P202 P206 P205 P159 P169 P194 P204 P175 P174 P184 P183 P176 P191 P201 P107 P106 P109 P108 P113 P112 P116 P115 P120 P119 P123 P122 P127 P126 P129 P128
Bank 0 0 0 0 0 0 0 0 0
Type I/O VREF I/O I/O I/O DUAL I/O INPUT INPUT INPUT INPUT INPUT INPUT GCLK GCLK VCCO VCCO VCCO DUAL DUAL DUAL DUAL VREF I/O I/O I/O DUAL DUAL VREF I/O RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL
Pinout Table
Table 17: PQ208 Package Pinout
XC3S250E XC3S500E Pin Name IO IO/VREF_0 IO_L01N_0 IO_L01P_0 IO_L02N_0/VREF_0 IO_L02P_0 IO_L03N_0 IO_L03P_0 IO_L04N_0/VREF_0 IO_L04P_0 IO_L05N_0 IO_L05P_0 IO_L07N_0/GCLK5 IO_L07P_0/GCLK4 IO_L08N_0/GCLK7 IO_L08P_0/GCLK6 IO_L10N_0/GCLK11 IO_L10P_0/GCLK10 IO_L11N_0 IO_L11P_0 IO_L12N_0/VREF_0 IO_L12P_0 IO_L13N_0 PQ208 Pin P187 P179 P161 P160 P163 P162 P165 P164 P168 P167 P172 P171 P178 P177 P181 P180 P186 P185 P190 P189 P193 P192 P197
0 0 Type I/O VREF I/O I/O VREF I/O I/O I/O VREF I/O I/O I/O GCLK GCLK GCLK GCLK GCLK GCLK I/O I/O VREF I/O I/O 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Table 17: PQ208 Package Pinout
XC3S250E XC3S500E Pin Name IO_L09N_1/A5/RHCLK5 IO_L09P_1/A6/RHCLK4 IO_L10N_1/A3/RHCLK7 IO_L10P_1/A4/RHCLK6 IO_L11N_1/A1 IO_L11P_1/A2 IO_L12N_1/A0 IO_L12P_1 IO_L13N_1 IO_L13P_1 IO_L14N_1 IO_L14P_1 IO_L15N_1/LDC0 IO_L15P_1/HDC IO_L16N_1/LDC2 IO_L16P_1/LDC1 IP IP IP IP IP IP IP IP/VREF_1 VCCO_1 VCCO_1 VCCO_1 IO/D5 IO/M1 IO/VREF_2 IO_L01N_2/INIT_B IO_L01P_2/CSO_B IO_L03N_2/MOSI/CSI_B IO_L03P_2/DOUT/BUSY PQ208 Pin P133 P132 P135 P134 P138 P137 P140 P139 P145 P144 P147 P146 P151 P150 P153 P152 P110 P118 P124 P130 P142 P148 P154 P136 P114 P125 P143 P76 P84 P98 P56 P55 P61 P60
Table 17: PQ208 Package Pinout
XC3S250E XC3S500E Pin Name IO_L04N_2 IO_L04P_2 IO_L05N_2 IO_L05P_2 IO_L06N_2 IO_L06P_2 IO_L08N_2/D6/GCLK13 IO_L08P_2/D7/GCLK12 IO_L09N_2/D3/GCLK15 IO_L09P_2/D4/GCLK14 IO_L11N_2/D1/GCLK3 IO_L11P_2/D2/GCLK2 IO_L12N_2/DIN/D0 IO_L12P_2/M0 IO_L13N_2 IO_L13P_2 IO_L14N_2/A22 IO_L14P_2/A23 IO_L15N_2/A20 IO_L15P_2/A21 IO_L16N_2/VS1/A18 IO_L16P_2/VS2/A19 IO_L17N_2/CCLK IO_L17P_2/VS0/A17 IP IP IP IP_L02N_2 IP_L02P_2 IP_L07N_2/VREF_2 IP_L07P_2 IP_L10N_2/M2/GCLK1 IP_L10P_2/RDWR_B/ GCLK0 VCCO_2 PQ208 Pin P63 P62 P65 P64 P69 P68 P75 P74 P78 P77 P83 P82 P87 P86 P90 P89 P94 P93 P97 P96 P100 P99 P103 P102 P54 P91 P101 P58 P57 P72 P71 P81 P80 P59
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2
Type RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL DUAL DUAL DUAL I/O I/O I/O I/O I/O DUAL DUAL DUAL DUAL INPUT INPUT INPUT INPUT INPUT INPUT INPUT VREF VCCO VCCO VCCO DUAL DUAL VREF DUAL DUAL DUAL DUAL
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Type I/O I/O I/O I/O I/O I/O DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL DUAL I/O I/O DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL INPUT INPUT INPUT INPUT INPUT VREF INPUT DUAL/GCLK DUAL/GCLK VCCO
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Pinout Descriptions
Table 17: PQ208 Package Pinout
XC3S250E XC3S500E Pin Name VCCO_2 VCCO_2 IO/VREF_3 IO_L01N_3 IO_L01P_3 IO_L02N_3/VREF_3 IO_L02P_3 IO_L03N_3 IO_L03P_3 IO_L04N_3 IO_L04P_3 IO_L05N_3 IO_L05P_3 IO_L06N_3 IO_L06P_3 IO_L07N_3/LHCLK1 IO_L07P_3/LHCLK0 IO_L08N_3/LHCLK3 IO_L08P_3/LHCLK2 IO_L09N_3/LHCLK5 IO_L09P_3/LHCLK4 IO_L10N_3/LHCLK7 IO_L10P_3/LHCLK6 IO_L11N_3 IO_L11P_3 IO_L12N_3 IO_L12P_3 IO_L13N_3 IO_L13P_3 IO_L14N_3 IO_L14P_3 IO_L15N_3 IO_L15P_3 IO_L16N_3 PQ208 Pin P73 P88 P45 P3 P2 P5 P4 P9 P8 P12 P11 P16 P15 P19 P18 P23 P22 P25 P24 P29 P28 P31 P30 P34 P33 P36 P35 P40 P39 P42 P41 P48 P47 P50
Table 17: PQ208 Package Pinout
XC3S250E XC3S500E Pin Name IO_L16P_3 IP IP IP IP IP IP IP/VREF_3 VCCO_3 VCCO_3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND DONE PROG_B TCK PQ208 Pin P49 P6 P14 P26 P32 P43 P51 P20 P21 P38 P46 P10 P17 P27 P37 P52 P53 P70 P79 P85 P95 P105 P121 P131 P141 P156 P173 P182 P188 P198 P208 P104 P1 P158
Bank 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Type VCCO VCCO VREF I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Bank 3 3 3 3 3 3 3 3 3 3 3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX
Type I/O INPUT INPUT INPUT INPUT INPUT INPUT VREF VCCO VCCO VCCO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND CONFIG CONFIG JTAG
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Table 17: PQ208 Package Pinout
XC3S250E XC3S500E Pin Name TDI TDO TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT PQ208 Pin P207 P157 P155 P7 P44 P66 P92 P111 P149 P166 P195 P13
Table 17: PQ208 Package Pinout
XC3S250E XC3S500E Pin Name VCCINT VCCINT VCCINT PQ208 Pin P67 P117 P170
Bank VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT
Type JTAG JTAG JTAG VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT
Bank VCCINT VCCINT VCCINT
Type VCCINT VCCINT VCCINT
User I/Os by Bank
Table 18 indicates how the 158 available user-I/O pins are distributed between the four I/O banks on the PQ208 package.
Footprint Migration Differences
The XC3S250E and XC3S500E FPGAs have identical footprints in the PQ208 package. Designs can migrate between the XC3S250E and XC3S500E without further consideration.
Table 18: User I/Os Per Bank for the XC3S250E and XC3S500E in the PQ208 Package
Package Edge Top Right Bottom Left TOTAL Maximum I/O 38 40 40 40 158 All Possible I/O Pins by Type I/O 18 9 8 23 58 INPUT 6 7 6 6 25 DUAL 1 21 24 0 46 VREF 5 3 2 3 13 GCLK 8 0 0 8 16
I/O Bank 0 1 2 3
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Pinout Descriptions
PQ208 Footprint (Left)
187 IO 186 IO_L10N_0/GCLK11 185 IO_L10P_0/GCLK10 184 IP_L09N_0/GCLK9 74 75 76 77 IO/D5 IO_L09P_2/D4/GCLK14 IO_L08P_2/D7/GCLK12 IO_L08N_2/D6/GCLK13 203 IO_L15N_0 202 IO_L15P_0 201 VCCO_0 200 IO_L14N_0/VREF_0 199 IO_L14P_0 193 IO_L12N_0/VREF_0 192 IO_L12P_0 191 VCCO_0 GND TDI IO_L16N_0/HSWAP IO_L16P_0 IP 183 IP_L09P_0/GCLK8 182 GND 78 IO_L09N_2/D3/GCLK15 GND 79
198 GND 197 IO_L13N_0 196 IO_L13P_0 195 VCCAUX 194 IP
PROG_B IO_L01P_3 IO_L01N_3 IO_L02P_3 IO_L02N_3/VREF_3 IP VCCAUX IO_L03P_3 IO_L03N_3 GND IO_L04P_3 IO_L04N_3 VCCINT IP IO_L05P_3 IO_L05N_3 GND IO_L06P_3 IO_L06N_3 IP/VREF_3 VCCO_3 IO_L07P_3/LHCLK0 IO_L07N_3/LHCLK1 IO_L08P_3/LHCLK2 IO_L08N_3/LHCLK3 IP GND IO_L09P_3/LHCLK4 IO_L09N_3/LHCLK5 IO_L10P_3/LHCLK6 IO_L10N_3/LHCLK7 IP IO_L11P_3 IO_L11N_3 IO_L12P_3 IO_L12N_3 GND VCCO_3 IO_L13P_3 IO_L13N_3 IO_L14P_3 IO_L14N_3 IP VCCAUX IO/VREF_3 VCCO_3 IO_L15P_3 IO_L15N_3 IO_L16P_3 IO_L16N_3 IP GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Bank 0
Bank 3
Bank 2
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 IP_L07P_2 IP_L07N_2/VREF_2 IP_L02N_2 VCCO_2 IO_L03P_2/DOUT/BUSY GND IP IO_L01P_2/CSO_B IO_L01N_2/INIT_B IP_L02P_2 IO_L04N_2 IO_L05P_2 IO_L05N_2 IO_L06N_2 GND IO_L03N_2/MOSI/CSI_B IO_L04P_2 IO_L06P_2 VCCAUX VCCINT VCCO_2 73
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Figure 5: PQ208 Footprint (Left)
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190 IO_L11N_0 189 IO_L11P_0 188 GND
208 207 206 205 204
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PQ208 Footprint (Right)
181 IO_L08N_0/GCLK7 180 IO_L08P_0/GCLK6 179 IO/VREF_0 178 IO_L07N_0/GCLK5 177 IO_L07P_0/GCLK4 176 VCCO_0 175 IP_L06N_0 174 IP_L06P_0 173 GND 172 IO_L05N_0 IO_L05P_0 VCCINT IP IO_L04N_0/VREF_0 IO_L04P_0 VCCAUX IO_L03N_0 IO_L03P_0 IO_L02N_0/VREF_0 IO_L02P_0
161 IO_L01N_0 160 IO_L01P_0 159 IP 158 TCK
157 TDO 156 GND 155 TMS 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 IP IO_L16N_1/LDC2 IO_L16P_1/LDC1 IO_L15N_1/LDC0 IO_L15P_1/HDC VCCAUX IP IO_L14N_1 IO_L14P_1 IO_L13N_1 IO_L13P_1 VCCO_1 IP GND IO_L12N_1/A0 IO_L12P_1 IO_L11N_1/A1 IO_L11P_1/A2 IP/VREF_1 IO_L10N_1/A3/RHCLK7 IO_L10P_1/A4/RHCLK6 IO_L09N_1/A5/RHCLK5 IO_L09P_1/A6/RHCLK4 GND IP IO_L08N_1/A7/RHCLK3 IO_L08P_1/A8/RHCLK2 IO_L07N_1/A9/RHCLK1 IO_L07P_1/A10/RHCLK VCCO_1 IP IO_L06N_1/VREF_1 IO_L06P_1 GND IO_L05N_1/A11 IO_L05P_1/A12 IP VCCINT IO_L04N_1 IO_L04P_1 VCCO_1 IO_L03N_1/VREF_1 IO_L03P_1 VCCAUX IP IO_L02N_1/A13 IO_L02P_1/A14 IO_L01N_1/A15 IO_L01P_1/A16 GND
Bank 0
171 170 169 168 167 166 165 164 163 162
Bank 2
80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 IO_L11P_2/D2/GCLK2 IO_L11N_2/D1/GCLK3 IO/M1 GND IO_L12P_2/M0 IO_L12N_2/DIN/D0 VCCO_2 IO_L13P_2 IP_L10P_2/RDWR_B/GCLK0 IP_L10N_2/M2/GCLK1 99 IO_L16N_2/VS1/A18 100 IP 101 IO_L17P_2/VS0/A17 102 IO_L17N_2/CCLK 103 DONE 104 IO_L13N_2 IO_L14N_2/A22 GND IO_L15P_2/A21 IO_L15N_2/A20 IO/VREF_2 IO_L16P_2/VS2/A19 IP VCCAUX IO_L14P_2/A23
Bank 1
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Figure 6: PQ208 Footprint (Right)
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Pinout Descriptions If the table row is highlighted in tan, then this is an instance where an unconnected pin on the XC3S250E FPGA maps to a VREF pin on the XC3S500E and XC3S1200E FPGA. If the FPGA application uses an I/O standard that requires a VREF voltage reference, connect the highlighted pin to the VREF voltage supply, even though this does not actually connect to the XC3S250E FPGA. This VREF connection on the board allows future migration to the larger devices without modifying the printed-circuit board. All other balls have nearly identical functionality on all three devices. Table 23 summarizes the Spartan-3E footprint migration differences for the FT256 package. An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx web site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
FT256: 256-ball Fine-pitch, Thin Ball Grid Array
The 256-lead fine-pitch, thin ball grid array package, FT256, supports three different Spartan-3E FPGAs, including the XC3S250E, the XC3S500E, and the XC3S1200E. Table 19 lists all the package pins. They are sorted by bank number and then by pin name of the largest device. Pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier. The highlighted rows indicate pinout differences between the XC3S250E, the XC3S500E, and the XC3S1200E FPGAs. The XC3S250E has 18 unconnected balls, indicated as N.C. (No Connection) in Table 19 and with the black diamond character ( ) in both Table 19 and in Figure 7.
Pinout Table
Table 19: FT256 Package Pinout
Bank 0 0 0 0 IO IO IO IP XC3S250E Pin Name IO IO IO IP XC3S500E Pin Name IO IO IO IO XC3S1200E Pin Name FT256 Ball A7 A12 B4 B6 Type I/O I/O I/O
250E: INPUT 500E: INPUT 1200E: I/O
0
IP
IP
IO
B10
250E: INPUT 500E: INPUT 1200E: I/O
0 0 0 0 0 0 0 0 0 0 0 0 0 0
IO/VREF_0 IO_L01N_0 IO_L01P_0 IO_L03N_0/VREF_0 IO_L03P_0 IO_L04N_0 IO_L04P_0 IO_L05N_0/VREF_0 IO_L05P_0 IO_L06N_0 IO_L06P_0 IO_L08N_0/GCLK5 IO_L08P_0/GCLK4 IO_L09N_0/GCLK7
IO/VREF_0 IO_L01N_0 IO_L01P_0 IO_L03N_0/VREF_0 IO_L03P_0 IO_L04N_0 IO_L04P_0 IO_L05N_0/VREF_0 IO_L05P_0 IO_L06N_0 IO_L06P_0 IO_L08N_0/GCLK5 IO_L08P_0/GCLK4 IO_L09N_0/GCLK7
IO/VREF_0 IO_L01N_0 IO_L01P_0 IO_L03N_0/VREF_0 IO_L03P_0 IO_L04N_0 IO_L04P_0 IO_L05N_0/VREF_0 IO_L05P_0 IO_L06N_0 IO_L06P_0 IO_L08N_0/GCLK5 IO_L08P_0/GCLK4 IO_L09N_0/GCLK7
D9 A14 B14 A13 B13 E11 D11 B11 C11 E10 D10 F9 E9 A9
VREF I/O I/O VREF I/O I/O I/O VREF I/O I/O I/O GCLK GCLK GCLK
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Table 19: FT256 Package Pinout (Continued)
Bank 0 0 0 0 0 0 XC3S250E Pin Name IO_L09P_0/GCLK6 IO_L11N_0/GCLK11 IO_L11P_0/GCLK10 IO_L12N_0 IO_L12P_0 N.C. ( ) XC3S500E Pin Name IO_L09P_0/GCLK6 IO_L11N_0/GCLK11 IO_L11P_0/GCLK10 IO_L12N_0 IO_L12P_0 IO_L13N_0 XC3S1200E Pin Name IO_L09P_0/GCLK6 IO_L11N_0/GCLK11 IO_L11P_0/GCLK10 IO_L12N_0 IO_L12P_0 IO_L13N_0 FT256 Ball A10 D8 C8 F8 E8 C7 Type GCLK GCLK GCLK I/O I/O
250E: N.C. 500E: I/O 1200E: I/O
0
N.C. ( )
IO_L13P_0
IO_L13P_0
B7
250E: N.C. 500E: I/O 1200E: I/O
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
IO_L14N_0/VREF_0 IO_L14P_0 IO_L15N_0 IO_L15P_0 IO_L17N_0/VREF_0 IO_L17P_0 IO_L18N_0 IO_L18P_0 IO_L19N_0/HSWAP IO_L19P_0 IP IP IP_L02N_0 IP_L02P_0 IP_L07N_0 IP_L07P_0 IP_L10N_0/GCLK9 IP_L10P_0/GCLK8 IP_L16N_0 IP_L16P_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 IO_L01N_1/A15
IO_L14N_0/VREF_0 IO_L14P_0 IO_L15N_0 IO_L15P_0 IO_L17N_0/VREF_0 IO_L17P_0 IO_L18N_0 IO_L18P_0 IO_L19N_0/HSWAP IO_L19P_0 IP IP IP_L02N_0 IP_L02P_0 IP_L07N_0 IP_L07P_0 IP_L10N_0/GCLK9 IP_L10P_0/GCLK8 IP_L16N_0 IP_L16P_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 IO_L01N_1/A15
IO_L14N_0/VREF_0 IO_L14P_0 IO_L15N_0 IO_L15P_0 IO_L17N_0/VREF_0 IO_L17P_0 IO_L18N_0 IO_L18P_0 IO_L19N_0/HSWAP IO_L19P_0 IP IP IP_L02N_0 IP_L02P_0 IP_L07N_0 IP_L07P_0 IP_L10N_0/GCLK9 IP_L10P_0/GCLK8 IP_L16N_0 IP_L16P_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 IO_L01N_1/A15
D7 E7 D6 C6 A4 A5 C4 C5 B3 C3 A3 C13 C12 D12 C9 C10 B8 A8 E6 D5 B5 B12 F7 F10 R15
VREF I/O I/O I/O VREF I/O I/O I/O DUAL I/O INPUT INPUT INPUT INPUT INPUT INPUT GCLK GCLK INPUT INPUT VCCO VCCO VCCO VCCO DUAL
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Table 19: FT256 Package Pinout (Continued)
Bank 1 1 1 1 XC3S250E Pin Name IO_L01P_1/A16 IO_L02N_1/A13 IO_L02P_1/A14 N.C. ( ) XC3S500E Pin Name IO_L01P_1/A16 IO_L02N_1/A13 IO_L02P_1/A14 IO_L03N_1/VREF_1 XC3S1200E Pin Name IO_L01P_1/A16 IO_L02N_1/A13 IO_L02P_1/A14 IO_L03N_1/VREF_1 FT256 Ball R16 P15 P16 N15 Type DUAL DUAL DUAL
250E: N.C. 500E: VREF 1200E: VREF
1
N.C. ( )
IO_L03P_1
IO_L03P_1
N14
250E: N.C. 500E: I/O 1200E: I/O
1 1 1
IO_L04N_1/VREF_1 IO_L04P_1 N.C. ( )
IO_L04N_1/VREF_1 IO_L04P_1 IO_L05N_1
IO_L04N_1/VREF_1 IO_L04P_1 IO_L05N_1
M16 N16 L13
VREF I/O
250E: N.C. 500E: I/O 1200E: I/O
1
N.C. ( )
IO_L05P_1
IO_L05P_1
L12
250E: N.C. 500E: I/O 1200E: I/O
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
IO_L06N_1 IO_L06P_1 IO_L07N_1/A11 IO_L07P_1/A12 IO_L08N_1/VREF_1 IO_L08P_1 IO_L09N_1/A9/RHCLK1 IO_L09P_1/A10/RHCLK0 IO_L10N_1/A7/RHCLK3/ TRDY1 IO_L10P_1/A8/RHCLK2 IO_L11N_1/A5/RHCLK5 IO_L11P_1/A6/RHCLK4/ IRDY1 IO_L12N_1/A3/RHCLK7 IO_L12P_1/A4/RHCLK6 IO_L13N_1/A1 IO_L13P_1/A2 IO_L14N_1/A0 IO_L14P_1 IO_L15N_1
IO_L06N_1 IO_L06P_1 IO_L07N_1/A11 IO_L07P_1/A12 IO_L08N_1/VREF_1 IO_L08P_1 IO_L09N_1/A9/RHCLK1 IO_L09P_1/A10/RHCLK0 IO_L10N_1/A7/RHCLK3/ TRDY1 IO_L10P_1/A8/RHCLK2 IO_L11N_1/A5/RHCLK5 IO_L11P_1/A6/RHCLK4/ IRDY1 IO_L12N_1/A3/RHCLK7 IO_L12P_1/A4/RHCLK6 IO_L13N_1/A1 IO_L13P_1/A2 IO_L14N_1/A0 IO_L14P_1 IO_L15N_1
IO_L06N_1 IO_L06P_1 IO_L07N_1/A11 IO_L07P_1/A12 IO_L08N_1/VREF_1 IO_L08P_1 IO_L09N_1/A9/RHCLK1 IO_L09P_1/A10/RHCLK0 IO_L10N_1/A7/RHCLK3/ TRDY1 IO_L10P_1/A8/RHCLK2 IO_L11N_1/A5/RHCLK5 IO_L11P_1/A6/RHCLK4/ IRDY1 IO_L12N_1/A3/RHCLK7 IO_L12P_1/A4/RHCLK6 IO_L13N_1/A1 IO_L13P_1/A2 IO_L14N_1/A0 IO_L14P_1 IO_L15N_1
L15 L14 K12 K13 K14 K15 J16 K16 J13 J14 H14 H15 H11 H12 G16 G15 G14 G13 F15
I/O I/O DUAL DUAL VREF I/O RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL DUAL DUAL DUAL I/O I/O
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Table 19: FT256 Package Pinout (Continued)
Bank 1 1 1 1 XC3S250E Pin Name IO_L15P_1 IO_L16N_1 IO_L16P_1 N.C. ( ) XC3S500E Pin Name IO_L15P_1 IO_L16N_1 IO_L16P_1 IO_L17N_1 XC3S1200E Pin Name IO_L15P_1 IO_L16N_1 IO_L16P_1 IO_L17N_1 FT256 Ball F14 F12 F13 E16 Type I/O I/O I/O
250E: N.C. 500E: I/O 1200E: I/O
1
N.C. ( ).
IO_L17P_1
IO_L17P_1
E13
250E: N.C. 500E: I/O 1200E: I/O
1 1 1 1 1 1 1 1 1 1 1 1
IO_L18N_1/LDC0 IO_L18P_1/HDC IO_L19N_1/LDC2 IO_L19P_1/LDC1 IP IP IP IP IP IP IP IO
IO_L18N_1/LDC0 IO_L18P_1/HDC IO_L19N_1/LDC2 IO_L19P_1/LDC1 IP IP IP IP IP IP IP IO
IO_L18N_1/LDC0 IO_L18P_1/HDC IO_L19N_1/LDC2 IO_L19P_1/LDC1 IP IP IP IP IP IP IP IP
D14 D15 C15 C16 B16 E14 G12 H16 J11 J12 M13 M14
DUAL DUAL DUAL DUAL INPUT INPUT INPUT INPUT INPUT INPUT INPUT
250E: I/O 500E: I/O 1200E: INPUT
1
IO/VREF_1
IP/VREF_1
IP/VREF_1
D16
250E: VREF(I/O) 500E: VREF(INPUT) 1200E: VREF(INPUT)
1 1 1 1 1 2
IP/VREF_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 IP
IP/VREF_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 IP
IP/VREF_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 IO
H13 E15 G11 K11 M15 M7
VREF VCCO VCCO VCCO VCCO
250E: INPUT 500E: INPUT 1200E: I/O
2
IP
IP
IO
T12
250E: INPUT 500E: INPUT 1200E: I/O
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Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 XC3S250E Pin Name IO/D5 IO/M1 IO/VREF_2 IO/VREF_2 IO_L01N_2/INIT_B IO_L01P_2/CSO_B IO_L03N_2/MOSI/CSI_B IO_L03P_2/DOUT/BUSY IO_L04N_2 IO_L04P_2 IO_L05N_2 IO_L05P_2 IO_L06N_2 IO_L06P_2 N.C. ( ) XC3S500E Pin Name IO/D5 IO/M1 IO/VREF_2 IO/VREF_2 IO_L01N_2/INIT_B IO_L01P_2/CSO_B IO_L03N_2/MOSI/CSI_B IO_L03P_2/DOUT/BUSY IO_L04N_2 IO_L04P_2 IO_L05N_2 IO_L05P_2 IO_L06N_2 IO_L06P_2 IO_L07N_2 XC3S1200E Pin Name IO/D5 IO/M1 IO/VREF_2 IO/VREF_2 IO_L01N_2/INIT_B IO_L01P_2/CSO_B IO_L03N_2/MOSI/CSI_B IO_L03P_2/DOUT/BUSY IO_L04N_2 IO_L04P_2 IO_L05N_2 IO_L05P_2 IO_L06N_2 IO_L06P_2 IO_L07N_2 FT256 Ball T8 T10 P13 R4 P4 P3 N5 P5 T5 T4 N6 M6 P6 R6 P7 Type DUAL DUAL VREF VREF DUAL DUAL DUAL DUAL I/O I/O I/O I/O I/O I/O
250E: N.C. 500E: I/O 1200E: I/O
2
N.C. ( )
IO_L07P_2
IO_L07P_2
N7
250E: N.C. 500E: I/O 1200E: I/O
2 2 2 2 2 2 2 2 2
IO_L09N_2/D6/GCLK13 IO_L09P_2/D7/GCLK12 IO_L10N_2/D3/GCLK15 IO_L10P_2/D4/GCLK14 IO_L12N_2/D1/GCLK3 IO_L12P_2/D2/GCLK2 IO_L13N_2/DIN/D0 IO_L13P_2/M0 N.C. ( )
IO_L09N_2/D6/GCLK13 IO_L09P_2/D7/GCLK12 IO_L10N_2/D3/GCLK15 IO_L10P_2/D4/GCLK14 IO_L12N_2/D1/GCLK3 IO_L12P_2/D2/GCLK2 IO_L13N_2/DIN/D0 IO_L13P_2/M0 IO_L14N_2/VREF_2
IO_L09N_2/D6/GCLK13 IO_L09P_2/D7/GCLK12 IO_L10N_2/D3/GCLK15 IO_L10P_2/D4/GCLK14 IO_L12N_2/D1/GCLK3 IO_L12P_2/D2/GCLK2 IO_L13N_2/DIN/D0 IO_L13P_2/M0 IO_L14N_2/VREF_2
L8 M8 P8 N8 N9 P9 M9 L9 R10
DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL DUAL
250E: N.C. 500E: VREF 1200E: VREF
2
N.C. ( )
IO_L14P_2
IO_L14P_2
P10
250E: N.C. 500E: I/O 1200E: I/O
2 2 2
IO_L15N_2 IO_L15P_2 IO_L16N_2/A22
IO_L15N_2 IO_L15P_2 IO_L16N_2/A22
IO_L15N_2 IO_L15P_2 IO_L16N_2/A22
M10 N10 P11
I/O I/O DUAL
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Table 19: FT256 Package Pinout (Continued)
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 XC3S250E Pin Name IO_L16P_2/A23 IO_L18N_2/A20 IO_L18P_2/A21 IO_L19N_2/VS1/A18 IO_L19P_2/VS2/A19 IO_L20N_2/CCLK IO_L20P_2/VS0/A17 IP IP IP_L02N_2 IP_L02P_2 IP_L08N_2/VREF_2 IP_L08P_2 IP_L11N_2/M2/GCLK1 IP_L11P_2/RDWR_B/ GCLK0 IP_L17N_2 IP_L17P_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 IO_L01N_3 IO_L01P_3 IO_L02N_3/VREF_3 IO_L02P_3 IO_L03N_3 IO_L03P_3 N.C. ( ) XC3S500E Pin Name IO_L16P_2/A23 IO_L18N_2/A20 IO_L18P_2/A21 IO_L19N_2/VS1/A18 IO_L19P_2/VS2/A19 IO_L20N_2/CCLK IO_L20P_2/VS0/A17 IP IP IP_L02N_2 IP_L02P_2 IP_L08N_2/VREF_2 IP_L08P_2 IP_L11N_2/M2/GCLK1 IP_L11P_2/RDWR_B/ GCLK0 IP_L17N_2 IP_L17P_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 IO_L01N_3 IO_L01P_3 IO_L02N_3/VREF_3 IO_L02P_3 IO_L03N_3 IO_L03P_3 IO_L04N_3/VREF_3 XC3S1200E Pin Name IO_L16P_2/A23 IO_L18N_2/A20 IO_L18P_2/A21 IO_L19N_2/VS1/A18 IO_L19P_2/VS2/A19 IO_L20N_2/CCLK IO_L20P_2/VS0/A17 IP IP IP_L02N_2 IP_L02P_2 IP_L08N_2/VREF_2 IP_L08P_2 IP_L11N_2/M2/GCLK1 IP_L11P_2/RDWR_B/ GCLK0 IP_L17N_2 IP_L17P_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 IO_L01N_3 IO_L01P_3 IO_L02N_3/VREF_3 IO_L02P_3 IO_L03N_3 IO_L03P_3 IO_L04N_3/VREF_3 FT256 Ball R11 N12 P12 R13 T13 R14 P14 T2 T14 R3 T3 T7 R7 R9 T9 M11 N11 L7 L10 R5 R12 B2 B1 C2 C1 E4 E3 F4 Type DUAL DUAL DUAL DUAL DUAL DUAL DUAL INPUT INPUT INPUT INPUT VREF INPUT DUAL/GCLK DUAL/GCLK INPUT INPUT VCCO VCCO VCCO VCCO I/O I/O VREF I/O I/O I/O
250E: N.C. 500E: VREF 1200E: VREF
3
N.C. ( )
IO_L04P_3
IO_L04P_3
F3
250E: N.C. 500E: I/O 1200E: I/O
3 3
IO_L05N_3 IO_L05P_3
IO_L05N_3 IO_L05P_3
IO_L05N_3 IO_L05P_3
E1 D1
I/O I/O
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Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 XC3S250E Pin Name IO_L06N_3 IO_L06P_3 IO_L07N_3 IO_L07P_3 IO_L08N_3/LHCLK1 IO_L08P_3/LHCLK0 IO_L09N_3/LHCLK3/ IRDY2 IO_L09P_3/LHCLK2 IO_L10N_3/LHCLK5 IO_L10P_3/LHCLK4/ TRDY2 IO_L11N_3/LHCLK7 IO_L11P_3/LHCLK6 IO_L12N_3 IO_L12P_3 IO_L13N_3 IO_L13P_3 N.C. ( ) XC3S500E Pin Name IO_L06N_3 IO_L06P_3 IO_L07N_3 IO_L07P_3 IO_L08N_3/LHCLK1 IO_L08P_3/LHCLK0 IO_L09N_3/LHCLK3/ IRDY2 IO_L09P_3/LHCLK2 IO_L10N_3/LHCLK5 IO_L10P_3/LHCLK4/ TRDY2 IO_L11N_3/LHCLK7 IO_L11P_3/LHCLK6 IO_L12N_3 IO_L12P_3 IO_L13N_3 IO_L13P_3 IO_L14N_3/VREF_3 XC3S1200E Pin Name IO_L06N_3 IO_L06P_3 IO_L07N_3 IO_L07P_3 IO_L08N_3/LHCLK1 IO_L08P_3/LHCLK0 IO_L09N_3/LHCLK3/ IRDY2 IO_L09P_3/LHCLK2 IO_L10N_3/LHCLK5 IO_L10P_3/LHCLK4/ TRDY2 IO_L11N_3/LHCLK7 IO_L11P_3/LHCLK6 IO_L12N_3 IO_L12P_3 IO_L13N_3 IO_L13P_3 IO_L14N_3/VREF_3 FT256 Ball G4 G5 G2 G3 H6 H5 H4 H3 J3 J2 J4 J5 K1 J1 K3 K2 L2 Type I/O I/O I/O I/O LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK I/O I/O I/O I/O
250E: N.C. 500E: VREF 1200E: VREF
3
N.C. ( )
IO_L14P_3
IO_L14P_3
L3
250E: N.C. 500E: I/O 1200E: I/O
3 3 3 3 3
IO_L15N_3 IO_L15P_3 IO_L16N_3 IO_L16P_3 N.C. ( )
IO_L15N_3 IO_L15P_3 IO_L16N_3 IO_L16P_3 IO_L17N_3
IO_L15N_3 IO_L15P_3 IO_L16N_3 IO_L16P_3 IO_L17N_3
L5 K5 N1 M1 L4
I/O I/O I/O I/O
250E: N.C. 500E: I/O 1200E: I/O
3
N.C. ( )
IO_L17P_3
IO_L17P_3
M4
250E: N.C. 500E: I/O 1200E: I/O
3 3 3 3
IO_L18N_3 IO_L18P_3 IO_L19N_3 IO_L19P_3
IO_L18N_3 IO_L18P_3 IO_L19N_3 IO_L19P_3
IO_L18N_3 IO_L18P_3 IO_L19N_3 IO_L19P_3
P1 P2 R1 R2
I/O I/O I/O I/O
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Pinout Descriptions
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Table 19: FT256 Package Pinout (Continued)
Bank 3 3 3 IP IP IO XC3S250E Pin Name IP IP IO XC3S500E Pin Name IP IP IP XC3S1200E Pin Name FT256 Ball D2 F2 F5 Type INPUT INPUT
250E: I/O 500E: I/O 1200E: INPUT
3 3 3 3 3 3 3
IP IP IP IP IP IP/VREF_3 IO/VREF_3
IP IP IP IP IP IP/VREF_3 IO/VREF_3
IP IP IP IP IP IP/VREF_3 IP/VREF_3
H1 J6 K4 M3 N3 G1 N2
INPUT INPUT INPUT INPUT INPUT VREF
250E: VREF(I/O) 500E: VREF(I/O) 1200E: VREF(INPUT)
3 3 3 3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
VCCO_3 VCCO_3 VCCO_3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
VCCO_3 VCCO_3 VCCO_3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
VCCO_3 VCCO_3 VCCO_3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
E2 G6 K6 M2 A1 A16 B9 F6 F11 G7 G8 G9 G10 H2 H7 H8 H9 H10 J7 J8 J9
VCCO VCCO VCCO VCCO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
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Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
Bank GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT XC3S250E Pin Name GND GND GND GND GND GND GND GND GND GND GND DONE PROG_B TCK TDI TDO TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT XC3S500E Pin Name GND GND GND GND GND GND GND GND GND GND GND DONE PROG_B TCK TDI TDO TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT XC3S1200E Pin Name GND GND GND GND GND GND GND GND GND GND GND DONE PROG_B TCK TDI TDO TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT FT256 Ball J10 J15 K7 K8 K9 K10 L6 L11 R8 T1 T16 T15 D3 A15 A2 C14 B15 A6 A11 F1 F16 L1 L16 T6 T11 D4 D13 E5 E12 M5 M12 N4 N13 Type GND GND GND GND GND GND GND GND GND GND GND CONFIG CONFIG JTAG JTAG JTAG JTAG VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
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Pinout Descriptions
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User I/Os by Bank
Table 20, Table 21, and Table 22 indicate how the available user-I/O pins are distributed between the four I/O banks on the FT256 package.
The XC3S250E FPGA in the FT256 package has 18 unconnected balls, labeled with an "N.C." type. These pins are also indicated with the black diamond ( ) symbol in Figure 7.
Table 20: User I/Os Per Bank on XC3S250E in the FT256 Package
Package Edge Top Right Bottom Left TOTAL Maximum I/O 44 42 44 42 172 All Possible I/O Pins by Type I/O 20 10 8 24 62 INPUT 10 7 9 7 33 DUAL 1 21 24 0 46 VREF 5 4 3 3 15 GCLK 8 0 0 8 16
I/O Bank 0 1 2 3
Table 21: User I/Os Per Bank on XC3S500E in the FT256 Package
Package Edge Top Right Bottom Left TOTAL Maximum I/O 46 48 48 48 190 All Possible I/O Pins by Type I/O 22 15 11 28 76 INPUT 10 7 9 7 33 DUAL 1 21 24 0 46 VREF 5 5 4 5 19 GCLK 8 0 0 8 16
I/O Bank 0 1 2 3
Table 22: User I/Os Per Bank on XC3S1200E in the FT256 Package
Package Edge Top Right Bottom Left TOTAL Maximum I/O 46 48 48 48 190 All Possible I/O Pins by Type I/O 24 14 13 27 78 INPUT 8 8 7 8 31 DUAL 1 21 24 0 46 VREF 5 5 4 5 19 GCLK 8 0 0 8 16
I/O Bank 0 1 2 3
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Pinout Descriptions and the XC3S1200E. The arrows indicate the direction for easy migration. A double-ended arrow ( ) indicates that the two pins have identical functionality. A left-facing arrow ( ) indicates that the pin on the device on the right unconditionally migrates to the pin on the device on the left. It may be possible to migrate the opposite direction depending on the I/O configuration. For example, an I/O pin (Type = I/O) can migrate to an input-only pin (Type = INPUT) if the I/O pin is configured as an input.
Footprint Migration Differences
Table 23 summarizes any footprint and functionality differences between the XC3S250E, the XC3S500E, and the XC3S1200E FPGAs that may affect easy migration between devices in the FG256 package. There are 26 such balls. All other pins not listed in Table 23 unconditionally migrate between Spartan-3E devices available in the FT256 package. The XC3S250E is duplicated on both the left and right sides of the table to show migrations to and from the XC3S500E
Table 23: FT256 Footprint Migration Differences
FT256 Ball B6 B7 B10 C7 D16 E13 E16 F3 F4 F5 L2 L3 L4 L12 L13 M4 M7 M14 N2 N7 N14 N15 P7 P10 R10 T12
Legend:
This pin is identical on both the device on the left and the right. This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be possible depending on how the pin is configured for the device on the right. This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be possible depending on how the pin is configured for the device on the left.
Bank 0 0 0 0 1 1 1 3 3 3 3 3 3 1 1 3 2 1 3 2 1 1 2 2 2 2
XC3S250E Type INPUT N.C. INPUT N.C. VREF(I/O) N.C. N.C. N.C. N.C. I/O N.C. N.C. N.C. N.C. N.C. N.C. INPUT I/O VREF(I/O) N.C. N.C. N.C. N.C. N.C. N.C. INPUT
Migration
XC3S500E Type INPUT I/O INPUT I/O VREF(INPUT) I/O I/O I/O VREF I/O VREF I/O I/O I/O I/O I/O INPUT I/O VREF(I/O) I/O I/O VREF I/O I/O VREF INPUT
Migration
XC3S1200E Type I/O I/O I/O I/O VREF(INPUT) I/O I/O I/O VREF INPUT VREF I/O I/O I/O I/O I/O I/O INPUT VREF(INPUT) I/O I/O VREF I/O I/O VREF I/O
Migration
XC3S250E Type INPUT N.C. INPUT N.C. VREF(I/O) N.C. N.C. N.C. N.C. I/O N.C. N.C. N.C. N.C. N.C. N.C. INPUT I/O VREF(I/O) N.C. N.C. N.C. N.C. N.C. N.C. INPUT
DIFFERENCES
19
7
26
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Pinout Descriptions
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FT256 Footprint
Bank 0 8 9
INPUT
VCCAUX
1 A
GND
2
TDI
3
INPUT I/O
L19N_0 HSWAP
4
I/O
L17N_0 VREF_0
5
I/O
L17P_0
6
7
I/O I/O
L13P_0
10
I/O
L09P_0 GCLK6
11
VCCAUX
12
I/O
13
I/O
L03N_0 VREF_0
14
I/O
L01N_0
15
TCK
16
GND
I/O
L09N_0 GCLK7
L10P_0 GCLK8
B
I/O
L01P_3
I/O
L01N_3
I/O
VCCO_0
INPUT
INPUT
L10N_0 GCLK9
GND
INPUT
I/O
L05N_0 VREF_0 VCCO_0
I/O
L03P_0
I/O
L01P_0
TMS I/O
INPUT I/O
L19P_1 LDC1
C
I/O
L02P_3
I/O
L02N_3 VREF_3
I/O
L19P_0
I/O
L18N_0
I/O
L18P_0
I/O
L15P_0
I/O
L13N_0
I/O
L11P_0 GCLK10
INPUT
L07N_0
INPUT
L07P_0
I/O
L05P_0
INPUT
L02N_0
INPUT
TDO
L19N_1 LDC2
D
I/O
L05P_3
INPUT INPUT PROG_B VCCINT
L16P_0
I/O
L15N_0
I/O
L14N_0 VREF_0
I/O
L11N_0 GCLK11
I/O
VREF_0
I/O
L06P_0
I/O
L04P_0
INPUT
L02P_0
I/O VCCINT L18N_1
LDC0
I/O
L18P_1 HDC
INPUT
VREF_1
E
I/O
L05N_3
VCCO_3
I/O
L03P_3
I/O
L03N_3
VCCINT INPUT
INPUT
L16N_0
I/O
L14P_0
I/O
L12P_0
I/O
L08P_0 GCLK4
I/O
L06N_0
I/O
L04N_0
I/O VCCINT L17P_1 INPUT
VCCO_1
I/O
L17N_1
I/O
I/O
L04N_3 VREF_3
F
VCCAUX
INPUT
L04P_3
GND
VCCO_0
I/O
L12N_0
I/O
L08N_0 GCLK5 VCCO_0
GND
I/O
L16N_1
I/O
L16P_1
I/O
L15P_1
I/O
L15N_1
VCCAUX
G
INPUT
VREF_3
I/O
L07N_3
I/O
L07P_3
I/O
L06N_3
I/O
L06P_3
VCCO_3
GND
GND
GND
GND
VCCO_1
INPUT I/O
L12P_1 A4 RHCLK6
I/O
L14P_1
I/O
L14N_1 A0
I/O
L13P_1 A2 L11P_1 A6 RHCLK4 IRDY1
I/O
L13N_1 A1
I/O
I/O
L09N_3 LHCLK3 IRDY2
I/O
L08P_3 LHCLK0
I/O
L08N_3 LHCLK1
I/O GND GND GND GND
L12N_1 A3 RHCLK7
Bank 3
VREF_1
J
I/O
L12P_3
I/O
L10P_3 LHCLK4 TRDY2
I/O
L10N_3 LHCLK5
I/O
L11N_3 LHCLK7
I/O
L11P_3 LHCLK6
I/O INPUT GND GND GND GND INPUT INPUT I/O
VCCO_3 L10N_1 A7 RHCLK3 TRDY1
I/O
L10P_1 A8 RHCLK2
I/O GND
L09N_1 A9 RHCLK1
K
I/O
L12N_3
I/O
L13P_3
I/O
L13N_3
INPUT I/O
L17N_3
I/O
L15P_3
I/O
L07P_1 A12
I/O
L08N_1 VREF_1
GND
GND I/O
GND I/O
L13P_2 M0
GND
VCCO_1
L07N_1 A11
I/O
L08P_1
I/O
L09P_1 A10 RHCLK0 VCCAUX
I/O
I/O
L14P_3
L
VCCAUX
L14N_3 VREF_3
I/O
L15N_3
I/O
VCCO_2
I/O
L05N_1
GND
VCCO_2
L09N_2 D6 GCLK13
GND
L05P_1
I/O
L06P_1
I/O
L06N_1
M
I/O
L16P_3
I/O
VCCO_3
INPUT
L17P_3
VCCINT
I/O
L05P_2
INPUT
I/O
L09P_2 D7 GCLK12
I/O
L13N_2 DIN D0
I/O
L15N_2
INPUT
L17N_2
VCCINT INPUT I/O
L18N_2 A20
INPUT
I/O
VCCO_1 L04N_1 VREF_1
N
I/O
L16N_3
INPUT
VREF_3
I/O INPUT VCCINT L03N_2
MOSI CSI_B
I/O
L05N_2
I/O
L07P_2
I/O
L10P_2 D4 GCLK14
I/O
L12N_2 D1 GCLK3
I/O
L15P_2
INPUT
L17P_2
I/O VCCINT L03P_1 I/O
L20P_2 VS0 A17
I/O
L03N_1 VREF_1
I/O
L04P_1
P
I/O
L18N_3
I/O
L18P_3
I/O
L01P_2 CSO_B
I/O
L01N_2 INIT_B
I/O
L03P_2 DOUT BUSY VCCO_2
I/O
L06N_2
I/O
L07N_2
I/O
L10N_2 D3 GCLK15
I/O
L12P_2 D2 GCLK2
I/O
L14P_2
I/O
L16N_2 A22
I/O
L18P_2 A21
I/O
VREF_2
I/O
L02N_1 A13
I/O
L02P_1 A14
R
I/O
L19N_3
I/O
L19P_3
INPUT
L02N_2
I/O
VREF_2
I/O
L06P_2
INPUT
L08P_2
INPUT GND
L11N_2 M2 GCLK1
I/O
L14N_2 VREF_2
I/O
L16P_2 A23 VCCO_2
I/O
L19N_2 VS1 A18
I/O
L20N_2 CCLK
I/O
L01N_1 A15
I/O
L01P_1 A16
T
GND
INPUT
INPUT
L02P_2
I/O
L04P_2
I/O
L04N_2
INPUT
VCCAUX L08N_2 VREF_2
I/O
D5
INPUT
L11P_2 RDWR_B GCLK0
I/O
M1
VCCAUX
INPUT
I/O
L19P_2 VS2 A19
INPUT
DONE
GND
Bank 2
DS312-4_05_021705
Figure 7: FT256 Package Footprint (top view)
2 28 6
CONFIG: Dedicated configuration pins GND: Ground
4 16 18
JTAG: Dedicated JTAG port pins VCCO: Output voltage supply for bank Unconnected pins on XC3S250E
8 8
VCCINT: Internal core supply voltage (+1.2V) VCCAUX: Auxiliary supply voltage (+2.5V)
Migration Difference: For flexible package migration, use these pins as inputs.
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Bank 1
H INPUT
GND
L09P_3 LHCLK2
INPUT
I/O
L11N_1 A5 RHCLK5
I/O
INPUT
R
Pinout Descriptions If the table row is highlighted in tan, then this is an instance where an unconnected pin on the XC3S500E FPGA maps to a VREF pin on the XC3S1200E and XC3S1600E FPGA. If the FPGA application uses an I/O standard that requires a VREF voltage reference, connect the highlighted pin to the VREF voltage supply, even though this does not actually connect to the XC3S500E FPGA. This VREF connection on the board allows future migration to the larger devices without modifying the printed-circuit board. All other balls have nearly identical functionality on all three devices. Table 23 summarizes the Spartan-3E footprint migration differences for the FG320 package. An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx web site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
FG320: 320-ball Fine-pitch Ball Grid Array
The 320-lead fine-pitch ball grid array package, FG320, supports three different Spartan-3E FPGAs, including the XC3S500E, the XC3S1200E, and the XC3S1600E, as shown in Table 24 and Figure 8. The FG320 package is an 18 x 18 array of solder balls minus the four center balls. Table 24 lists all the package pins. They are sorted by bank number and then by pin name of the largest device. Pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier. The highlighted rows indicate pinout differences between the XC3S500E, the XC3S1200E, and the XC3S1600E FPGAs. The XC3S500E has 18 unconnected balls, indicated as N.C. (No Connection) in Table 24 and with the black diamond character ( ) in both Table 24 and in Figure 8.
Pinout Table
Table 24: FG320 Package Pinout
Bank 0 IP XC3S500E Pin Name IO XC3S1200E Pin Name IO XC3S1600E Pin Name FG320 Ball A7 Type 500E: INPUT 1200E: I/O 1600E: I/O 0 0 0 0 IO IO IO IP IO IO IO IO IO IO IO IO A8 A11 C4 D13 I/O I/O I/O 500E: INPUT 1200E: I/O 1600E: I/O 0 0 0 0 0 0 0 0 0 0 0 0 0 IO IO IO/VREF_0 IO_L01N_0 IO_L01P_0 IO_L03N_0/VREF_0 IO_L03P_0 IO_L04N_0 IO_L04P_0 IO_L05N_0/VREF_0 IO_L05P_0 IO_L06N_0 IO_L06P_0 IO IO IO/VREF_0 IO_L01N_0 IO_L01P_0 IO_L03N_0/VREF_0 IO_L03P_0 IO_L04N_0 IO_L04P_0 IO_L05N_0/VREF_0 IO_L05P_0 IO_L06N_0 IO_L06P_0 IO IO IO/VREF_0 IO_L01N_0 IO_L01P_0 IO_L03N_0/VREF_0 IO_L03P_0 IO_L04N_0 IO_L04P_0 IO_L05N_0/VREF_0 IO_L05P_0 IO_L06N_0 IO_L06P_0 E13 G9 B11 A16 B16 C14 D14 A14 B14 B13 A13 E12 F12 I/O I/O VREF I/O I/O VREF I/O I/O I/O VREF I/O I/O I/O
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Pinout Descriptions
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Table 24: FG320 Package Pinout (Continued)
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XC3S500E Pin Name IO_L08N_0 IO_L08P_0 IO_L09N_0 IO_L09P_0 IO_L11N_0/GCLK5 IO_L11P_0/GCLK4 IO_L12N_0/GCLK7 IO_L12P_0/GCLK6 IO_L14N_0/GCLK11 IO_L14P_0/GCLK10 IO_L15N_0 IO_L15P_0 IO_L17N_0 IO_L17P_0 IO_L18N_0/VREF_0 IO_L18P_0 IO_L19N_0/VREF_0 IO_L19P_0 IO_L20N_0 IO_L20P_0 N.C. ( ) XC3S1200E Pin Name IO_L08N_0 IO_L08P_0 IO_L09N_0 IO_L09P_0 IO_L11N_0/GCLK5 IO_L11P_0/GCLK4 IO_L12N_0/GCLK7 IO_L12P_0/GCLK6 IO_L14N_0/GCLK11 IO_L14P_0/GCLK10 IO_L15N_0 IO_L15P_0 IO_L17N_0 IO_L17P_0 IO_L18N_0/VREF_0 IO_L18P_0 IO_L19N_0/VREF_0 IO_L19P_0 IO_L20N_0 IO_L20P_0 IO_L21N_0 XC3S1600E Pin Name IO_L08N_0 IO_L08P_0 IO_L09N_0 IO_L09P_0 IO_L11N_0/GCLK5 IO_L11P_0/GCLK4 IO_L12N_0/GCLK7 IO_L12P_0/GCLK6 IO_L14N_0/GCLK11 IO_L14P_0/GCLK10 IO_L15N_0 IO_L15P_0 IO_L17N_0 IO_L17P_0 IO_L18N_0/VREF_0 IO_L18P_0 IO_L19N_0/VREF_0 IO_L19P_0 IO_L20N_0 IO_L20P_0 IO_L21N_0 FG320 Ball F11 E11 D11 C11 E10 D10 A10 B10 D9 C9 F9 E9 F8 E8 D7 C7 E7 F7 A6 B6 E6 Type I/O I/O I/O I/O GCLK GCLK GCLK GCLK GCLK GCLK I/O I/O I/O I/O VREF I/O VREF I/O I/O I/O 500E: N.C. 1200E: I/O 1600E: I/O 0 N.C. ( ) IO_L21P_0 IO_L21P_0 D6 500E: N.C. 1200E: I/O 1600E: I/O 0 0 0 0 0 0 0 0 IO_L23N_0/VREF_0 IO_L23P_0 IO_L24N_0 IO_L24P_0 IO_L25N_0/HSWAP IO_L25P_0 IP N.C. ( ) IO_L23N_0/VREF_0 IO_L23P_0 IO_L24N_0 IO_L24P_0 IO_L25N_0/HSWAP IO_L25P_0 IP IO IO_L23N_0/VREF_0 IO_L23P_0 IO_L24N_0 IO_L24P_0 IO_L25N_0/HSWAP IO_L25P_0 IP IP D5 C5 B4 A4 B3 C3 A3 A12 VREF I/O I/O I/O DUAL I/O INPUT 500E: N.C. 1200E: I/O 1600E: INPUT
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Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 IP IP_L02N_0 IP_L02P_0 IP_L07N_0 IP_L07P_0 IP_L10N_0 IP_L10P_0 IP_L13N_0/GCLK9 IP_L13P_0/GCLK8 IP_L16N_0 IP_L16P_0 IP_L22N_0 IP_L22P_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 N.C. ( ) XC3S500E Pin Name IP IP_L02N_0 IP_L02P_0 IP_L07N_0 IP_L07P_0 IP_L10N_0 IP_L10P_0 IP_L13N_0/GCLK9 IP_L13P_0/GCLK8 IP_L16N_0 IP_L16P_0 IP_L22N_0 IP_L22P_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 IO XC3S1200E Pin Name IP IP_L02N_0 IP_L02P_0 IP_L07N_0 IP_L07P_0 IP_L10N_0 IP_L10P_0 IP_L13N_0/GCLK9 IP_L13P_0/GCLK8 IP_L16N_0 IP_L16P_0 IP_L22N_0 IP_L22P_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 IO XC3S1600E Pin Name FG320 Ball C15 A15 B15 D12 C12 G10 F10 B9 B8 D8 C8 B5 A5 A9 C6 C13 G8 G11 P16 Type INPUT INPUT INPUT INPUT INPUT INPUT INPUT GCLK GCLK INPUT INPUT INPUT INPUT VCCO VCCO VCCO VCCO VCCO 500E: N.C. 1200E: I/O 1600E: I/O 1 1 1 1 1 1 1 IO_L01N_1/A15 IO_L01P_1/A16 IO_L02N_1/A13 IO_L02P_1/A14 IO_L03N_1/VREF_1 IO_L03P_1 N.C. ( ) IO_L01N_1/A15 IO_L01P_1/A16 IO_L02N_1/A13 IO_L02P_1/A14 IO_L03N_1/VREF_1 IO_L03P_1 IO_L04N_1 IO_L01N_1/A15 IO_L01P_1/A16 IO_L02N_1/A13 IO_L02P_1/A14 IO_L03N_1/VREF_1 IO_L03P_1 IO_L04N_1 T17 U18 T18 R18 R16 R15 N14 DUAL DUAL DUAL DUAL VREF I/O 500E: N.C. 1200E: I/O 1600E: INPUT 1 N.C. ( ) IO_L04P_1 IO_L04P_1 N15 500E: N.C. 1200E: I/O 1600E: INPUT 1 1 1 IO_L05N_1/VREF_1 IO_L05P_1 IO_L06N_1 IO_L05N_1/VREF_1 IO_L05P_1 IO_L06N_1 IO_L05N_1/VREF_1 IO_L05P_1 IO_L06N_1 M13 M14 P18 VREF I/O I/O
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Pinout Descriptions
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Table 24: FG320 Package Pinout (Continued)
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 XC3S500E Pin Name IO_L06P_1 IO_L07N_1 IO_L07P_1 IO_L08N_1 IO_L08P_1 IO_L09N_1/A11 IO_L09P_1/A12 IO_L10N_1/VREF_1 IO_L10P_1 IO_L11N_1/A9/RHCLK1 IO_L11P_1/A10/RHCLK0 IO_L12N_1/A7/RHCLK3/ TRDY1 IO_L12P_1/A8/RHCLK2 IO_L13N_1/A5/RHCLK5 IO_L13P_1/A6/RHCLK4/ IRDY1 IO_L14N_1/A3/RHCLK7 IO_L14P_1/A4/RHCLK6 IO_L15N_1/A1 IO_L15P_1/A2 IO_L16N_1/A0 IO_L16P_1 IO_L17N_1 IO_L17P_1 IO_L18N_1 IO_L18P_1 IO_L19N_1 IO_L19P_1 IO_L20N_1 IO_L20P_1 IO_L21N_1 IO_L21P_1 N.C. ( ) XC3S1200E Pin Name IO_L06P_1 IO_L07N_1 IO_L07P_1 IO_L08N_1 IO_L08P_1 IO_L09N_1/A11 IO_L09P_1/A12 IO_L10N_1/VREF_1 IO_L10P_1 IO_L11N_1/A9/RHCLK1 IO_L11P_1/A10/RHCLK0 IO_L12N_1/A7/RHCLK3/ TRDY1 IO_L12P_1/A8/RHCLK2 IO_L13N_1/A5/RHCLK5 IO_L13P_1/A6/RHCLK4/ IRDY1 IO_L14N_1/A3/RHCLK7 IO_L14P_1/A4/RHCLK6 IO_L15N_1/A1 IO_L15P_1/A2 IO_L16N_1/A0 IO_L16P_1 IO_L17N_1 IO_L17P_1 IO_L18N_1 IO_L18P_1 IO_L19N_1 IO_L19P_1 IO_L20N_1 IO_L20P_1 IO_L21N_1 IO_L21P_1 IO_L22N_1 XC3S1600E Pin Name IO_L06P_1 IO_L07N_1 IO_L07P_1 IO_L08N_1 IO_L08P_1 IO_L09N_1/A11 IO_L09P_1/A12 IO_L10N_1/VREF_1 IO_L10P_1 IO_L11N_1/A9/RHCLK1 IO_L11P_1/A10/RHCLK0 IO_L12N_1/A7/RHCLK3/ TRDY1 IO_L12P_1/A8/RHCLK2 IO_L13N_1/A5/RHCLK5 IO_L13P_1/A6/RHCLK4/ IRDY1 IO_L14N_1/A3/RHCLK7 IO_L14P_1/A4/RHCLK6 IO_L15N_1/A1 IO_L15P_1/A2 IO_L16N_1/A0 IO_L16P_1 IO_L17N_1 IO_L17P_1 IO_L18N_1 IO_L18P_1 IO_L19N_1 IO_L19P_1 IO_L20N_1 IO_L20P_1 IO_L21N_1 IO_L21P_1 IO_L22N_1 FG320 Ball P17 M16 M15 M18 N18 L15 L16 L17 L18 K12 K13 K14 K15 J16 J17 J14 J15 J13 J12 H17 H16 H15 H14 G16 G15 F17 F18 G13 G14 F14 F15 E16 Type I/O I/O I/O I/O I/O DUAL DUAL VREF I/O RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL RHCLK/DUAL DUAL DUAL DUAL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 500E: N.C. 1200E: I/O 1600E: I/O
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Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
Bank 1 XC3S500E Pin Name N.C. ( ) XC3S1200E Pin Name IO_L22P_1 XC3S1600E Pin Name IO_L22P_1 FG320 Ball E15 Type 500E: N.C. 1200E: I/O 1600E: I/O 1 1 1 1 1 1 IO_L23N_1/LDC0 IO_L23P_1/HDC IO_L24N_1/LDC2 IO_L24P_1/LDC1 IP IO IO_L23N_1/LDC0 IO_L23P_1/HDC IO_L24N_1/LDC2 IO_L24P_1/LDC1 IP IP IO_L23N_1/LDC0 IO_L23P_1/HDC IO_L24N_1/LDC2 IO_L24P_1/LDC1 IP IP D16 D17 C17 C18 B18 E17 DUAL DUAL DUAL DUAL INPUT 500E: I/O 1200E: INPUT 1600E: INPUT 1 1 1 1 1 1 1 1 1 IP IP IP IP IP IP IP IP IO IP IP IP IP IP IP IP IP IP IP IP IP IP IP IP IP IP IP E18 G18 H13 K17 K18 L13 L14 N17 P15 INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT 500E: I/O 1200E: INPUT 1600E: INPUT 1 1 1 1 1 1 1 1 2 2 2 IP IP/VREF_1 IP/VREF_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 IO IO IP IP IP/VREF_1 IP/VREF_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 IO IO IO IP IP/VREF_1 IP/VREF_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 IO IO IO R17 D18 H18 F16 H12 J18 L12 N16 P9 R11 U6 INPUT VREF VREF VCCO VCCO VCCO VCCO VCCO I/O I/O 500E: INPUT 1200E: I/O 1600E: I/O
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Pinout Descriptions
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Table 24: FG320 Package Pinout (Continued)
Bank 2 IP XC3S500E Pin Name IO XC3S1200E Pin Name IO XC3S1600E Pin Name FG320 Ball U13 Type 500E: INPUT 1200E: I/O 1600E: I/O 2 N.C. ( ) IO IO V7 500E: N.C. 1200E: I/O 1600E: I/O 2 2 2 2 2 2 2 2 2 2 2 2 2 IO/D5 IO/M1 IO/VREF_2 IO/VREF_2 IO_L01N_2/INIT_B IO_L01P_2/CSO_B IO_L03N_2/MOSI/CSI_B IO_L03P_2/DOUT/BUSY IO_L04N_2 IO_L04P_2 IO_L05N_2 IO_L05P_2 N.C. ( ) IO/D5 IO/M1 IO/VREF_2 IO/VREF_2 IO_L01N_2/INIT_B IO_L01P_2/CSO_B IO_L03N_2/MOSI/CSI_B IO_L03P_2/DOUT/BUSY IO_L04N_2 IO_L04P_2 IO_L05N_2 IO_L05P_2 IO_L06N_2/VREF_2 IO/D5 IO/M1 IO/VREF_2 IO/VREF_2 IO_L01N_2/INIT_B IO_L01P_2/CSO_B IO_L03N_2/MOSI/CSI_B IO_L03P_2/DOUT/BUSY IO_L04N_2 IO_L04P_2 IO_L05N_2 IO_L05P_2 IO_L06N_2/VREF_2 R9 V11 T15 U5 T3 U3 T4 U4 T5 R5 P6 R6 V6 DUAL DUAL VREF VREF DUAL DUAL DUAL DUAL I/O I/O I/O I/O 500E: N.C. 1200E: VREF 1600E: VREF 2 N.C. ( ) IO_L06P_2 IO_L06P_2 V5 500E: N.C. 1200E: I/O 1600E: I/O 2 2 2 2 2 2 2 2 2 2 2 2 2 IO_L07N_2 IO_L07P_2 IO_L09N_2 IO_L09P_2 IO_L10N_2 IO_L10P_2 IO_L12N_2/D6/GCLK13 IO_L12P_2/D7/GCLK12 IO_L13N_2/D3/GCLK15 IO_L13P_2/D4/GCLK14 IO_L15N_2/D1/GCLK3 IO_L15P_2/D2/GCLK2 IO_L16N_2/DIN/D0 IO_L07N_2 IO_L07P_2 IO_L09N_2 IO_L09P_2 IO_L10N_2 IO_L10P_2 IO_L12N_2/D6/GCLK13 IO_L12P_2/D7/GCLK12 IO_L13N_2/D3/GCLK15 IO_L13P_2/D4/GCLK14 IO_L15N_2/D1/GCLK3 IO_L15P_2/D2/GCLK2 IO_L16N_2/DIN/D0 IO_L07N_2 IO_L07P_2 IO_L09N_2 IO_L09P_2 IO_L10N_2 IO_L10P_2 IO_L12N_2/D6/GCLK13 IO_L12P_2/D7/GCLK12 IO_L13N_2/D3/GCLK15 IO_L13P_2/D4/GCLK14 IO_L15N_2/D1/GCLK3 IO_L15P_2/D2/GCLK2 IO_L16N_2/DIN/D0 P7 N7 N8 P8 T8 R8 M9 N9 V9 U9 P10 R10 N10 I/O I/O I/O I/O I/O I/O DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL/GCLK DUAL
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Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
Bank 2 2 2 2 2 2 2 2 XC3S500E Pin Name IO_L16P_2/M0 IO_L18N_2 IO_L18P_2 IO_L19N_2/VREF_2 IO_L19P_2 IO_L20N_2 IO_L20P_2 N.C. ( ) XC3S1200E Pin Name IO_L16P_2/M0 IO_L18N_2 IO_L18P_2 IO_L19N_2/VREF_2 IO_L19P_2 IO_L20N_2 IO_L20P_2 IO_L21N_2 XC3S1600E Pin Name IO_L16P_2/M0 IO_L18N_2 IO_L18P_2 IO_L19N_2/VREF_2 IO_L19P_2 IO_L20N_2 IO_L20P_2 IO_L21N_2 FG320 Ball M10 N11 P11 V13 V12 R12 T12 P12 Type DUAL I/O I/O VREF I/O I/O I/O 500E: N.C. 1200E: I/O 1600E: I/O 2 N.C. ( ) IO_L21P_2 IO_L21P_2 N12 500E: N.C. 1200E: I/O 1600E: I/O 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IO_L22N_2/A22 IO_L22P_2/A23 IO_L24N_2/A20 IO_L24P_2/A21 IO_L25N_2/VS1/A18 IO_L25P_2/VS2/A19 IO_L26N_2/CCLK IO_L26P_2/VS0/A17 IP IP IP_L02N_2 IP_L02P_2 IP_L08N_2 IP_L08P_2 IP_L11N_2/VREF_2 IP_L11P_2 IP_L14N_2/M2/GCLK1 IP_L14P_2/RDWR_B/ GCLK0 IP_L17N_2 IP_L17P_2 IP_L23N_2 IP_L23P_2 IO_L22N_2/A22 IO_L22P_2/A23 IO_L24N_2/A20 IO_L24P_2/A21 IO_L25N_2/VS1/A18 IO_L25P_2/VS2/A19 IO_L26N_2/CCLK IO_L26P_2/VS0/A17 IP IP IP_L02N_2 IP_L02P_2 IP_L08N_2 IP_L08P_2 IP_L11N_2/VREF_2 IP_L11P_2 IP_L14N_2/M2/GCLK1 IP_L14P_2/RDWR_B/ GCLK0 IP_L17N_2 IP_L17P_2 IP_L23N_2 IP_L23P_2 IO_L22N_2/A22 IO_L22P_2/A23 IO_L24N_2/A20 IO_L24P_2/A21 IO_L25N_2/VS1/A18 IO_L25P_2/VS2/A19 IO_L26N_2/CCLK IO_L26P_2/VS0/A17 IP IP IP_L02N_2 IP_L02P_2 IP_L08N_2 IP_L08P_2 IP_L11N_2/VREF_2 IP_L11P_2 IP_L14N_2/M2/GCLK1 IP_L14P_2/RDWR_B/ GCLK0 IP_L17N_2 IP_L17P_2 IP_L23N_2 IP_L23P_2 R13 P13 R14 T14 U15 V15 U16 T16 V2 V16 V3 V4 R7 T7 V8 U8 T10 U10 U11 T11 U14 V14 DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL INPUT INPUT INPUT INPUT INPUT INPUT VREF INPUT DUAL/GCLK DUAL/GCLK INPUT INPUT INPUT INPUT
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Pinout Descriptions
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Table 24: FG320 Package Pinout (Continued)
Bank 2 2 2 2 2 3 XC3S500E Pin Name VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 N.C. ( ) XC3S1200E Pin Name VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 IO XC3S1600E Pin Name VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 IO FG320 Ball M8 M11 T6 T13 V10 D4 Type VCCO VCCO VCCO VCCO VCCO 500E: N.C. 1200E: I/O 1600E: I/O 3 3 3 3 3 3 3 IO_L01N_3 IO_L01P_3 IO_L02N_3/VREF_3 IO_L02P_3 IO_L03N_3 IO_L03P_3 N.C. ( ) IO_L01N_3 IO_L01P_3 IO_L02N_3/VREF_3 IO_L02P_3 IO_L03N_3 IO_L03P_3 IO_L04N_3 IO_L01N_3 IO_L01P_3 IO_L02N_3/VREF_3 IO_L02P_3 IO_L03N_3 IO_L03P_3 IO_L04N_3 C2 C1 D2 D1 E1 E2 E3 I/O I/O VREF I/O I/O I/O 500E: N.C. 1200E: I/O 1600E: I/O 3 N.C. ( ) IO_L04P_3 IO_L04P_3 E4 500E: N.C. 1200E: I/O 1600E: I/O 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 IO_L05N_3 IO_L05P_3 IO_L06N_3/VREF_3 IO_L06P_3 IO_L07N_3 IO_L07P_3 IO_L08N_3 IO_L08P_3 IO_L09N_3 IO_L09P_3 IO_L10N_3 IO_L10P_3 IO_L11N_3/LHCLK1 IO_L11P_3/LHCLK0 IO_L12N_3/LHCLK3/ IRDY2 IO_L12P_3/LHCLK2 IO_L05N_3 IO_L05P_3 IO_L06N_3/VREF_3 IO_L06P_3 IO_L07N_3 IO_L07P_3 IO_L08N_3 IO_L08P_3 IO_L09N_3 IO_L09P_3 IO_L10N_3 IO_L10P_3 IO_L11N_3/LHCLK1 IO_L11P_3/LHCLK0 IO_L12N_3/LHCLK3/ IRDY2 IO_L12P_3/LHCLK2 IO_L05N_3 IO_L05P_3 IO_L06N_3/VREF_3 IO_L06P_3 IO_L07N_3 IO_L07P_3 IO_L08N_3 IO_L08P_3 IO_L09N_3 IO_L09P_3 IO_L10N_3 IO_L10P_3 IO_L11N_3/LHCLK1 IO_L11P_3/LHCLK0 IO_L12N_3/LHCLK3/ IRDY2 IO_L12P_3/LHCLK2 F2 F1 G4 G3 G5 G6 H5 H6 H3 H4 H1 H2 J4 J5 J2 J1 I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O LHCLK LHCLK LHCLK LHCLK
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Table 24: FG320 Package Pinout (Continued)
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 XC3S500E Pin Name IO_L13N_3/LHCLK5 IO_L13P_3/LHCLK4/ TRDY2 IO_L14N_3/LHCLK7 IO_L14P_3/LHCLK6 IO_L15N_3 IO_L15P_3 IO_L16N_3 IO_L16P_3 IO_L17N_3/VREF_3 IO_L17P_3 IO_L18N_3 IO_L18P_3 IO_L19N_3 IO_L19P_3 IO_L20N_3 IO_L20P_3 IO_L21N_3 IO_L21P_3 N.C. ( ) XC3S1200E Pin Name IO_L13N_3/LHCLK5 IO_L13P_3/LHCLK4/ TRDY2 IO_L14N_3/LHCLK7 IO_L14P_3/LHCLK6 IO_L15N_3 IO_L15P_3 IO_L16N_3 IO_L16P_3 IO_L17N_3/VREF_3 IO_L17P_3 IO_L18N_3 IO_L18P_3 IO_L19N_3 IO_L19P_3 IO_L20N_3 IO_L20P_3 IO_L21N_3 IO_L21P_3 IO_L22N_3 XC3S1600E Pin Name IO_L13N_3/LHCLK5 IO_L13P_3/LHCLK4/ TRDY2 IO_L14N_3/LHCLK7 IO_L14P_3/LHCLK6 IO_L15N_3 IO_L15P_3 IO_L16N_3 IO_L16P_3 IO_L17N_3/VREF_3 IO_L17P_3 IO_L18N_3 IO_L18P_3 IO_L19N_3 IO_L19P_3 IO_L20N_3 IO_L20P_3 IO_L21N_3 IO_L21P_3 IO_L22N_3 FG320 Ball K4 K3 K5 K6 L2 L1 L4 L3 L5 L6 M3 M4 M6 M5 N5 N4 P1 P2 P4 Type LHCLK LHCLK LHCLK LHCLK I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O 500E: N.C. 1200E: I/O 1600E: I/O 3 N.C. ( ) IO_L22P_3 IO_L22P_3 P3 500E: N.C. 1200E: I/O 1600E: I/O 3 3 3 3 3 3 IO_L23N_3 IO_L23P_3 IO_L24N_3 IO_L24P_3 IP IO IO_L23N_3 IO_L23P_3 IO_L24N_3 IO_L24P_3 IP IP IO_L23N_3 IO_L23P_3 IO_L24N_3 IO_L24P_3 IP IP R2 R3 T1 T2 D3 F4 I/O I/O I/O I/O INPUT 500E: I/O 1200E: INPUT 1600E: INPUT 3 3 3 3 IP IP IP IP IP IP IP IP IP IP IP IP F5 G1 J7 K2 INPUT INPUT INPUT INPUT
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Pinout Descriptions
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Table 24: FG320 Package Pinout (Continued)
Bank 3 3 3 3 3 3 3 3 IP IP IP IP IP IP IP/VREF_3 IO/VREF_3 XC3S500E Pin Name IP IP IP IP IP IP IP/VREF_3 IP/VREF_3 XC3S1200E Pin Name IP IP IP IP IP IP IP/VREF_3 IP/VREF_3 XC3S1600E Pin Name FG320 Ball K7 M1 N1 N2 R1 U1 J6 R4 Type INPUT INPUT INPUT INPUT INPUT INPUT VREF 500E: VREF(I/O) 1200E: VREF(INPUT) 1600E: VREF(INPUT) 3 3 3 3 3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND F3 H7 K1 L7 N3 A1 A18 B2 B17 C10 G7 G12 H8 H9 H10 H11 J3 J8 J11 K8 K11 K16 L8 L9 VCCO VCCO VCCO VCCO VCCO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
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Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
Bank GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT XC3S500E Pin Name GND GND GND GND GND GND GND GND GND DONE PROG_B TCK TDI TDO TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT XC3S1200E Pin Name GND GND GND GND GND GND GND GND GND DONE PROG_B TCK TDI TDO TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT XC3S1600E Pin Name GND GND GND GND GND GND GND GND GND DONE PROG_B TCK TDI TDO TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT FG320 Ball L10 L11 M7 M12 T9 U2 U17 V1 V18 V17 B1 A17 A2 C16 D15 B7 B12 G2 G17 M2 M17 U7 U12 E5 E14 F6 F13 N6 N13 P5 P14 Type GND GND GND GND GND GND GND GND GND CONFIG CONFIG JTAG JTAG JTAG JTAG VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
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Pinout Descriptions
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User I/Os by Bank
Table 25, Table 26, and Table 27 indicate how the available user-I/O pins are distributed between the four I/O banks on the FG320 package.
Table 25: User I/Os Per Bank for XC3S500E in the FG320 Package
Package Edge Top Right Bottom Left TOTAL Maximum I/O 58 58 58 58 232 All Possible I/O Pins by Type I/O 29 22 17 34 102 INPUT 14 10 13 11 48 DUAL 1 21 24 0 46 VREF 6 5 4 5 20 GCLK 8 0 0 8 16
I/O Bank 0 1 2 3
Table 26: User I/Os Per Bank for XC3S1200E in the FG320 Package
Package Edge Top Right Bottom Left TOTAL Maximum I/O 61 63 63 63 250 All Possible I/O Pins by Type I/O 34 25 23 38 120 INPUT 12 12 11 12 47 DUAL 1 21 24 0 46 VREF 6 5 5 5 21 GCLK 8 0 0 8 16
I/O Bank 0 1 2 3
Table 27: User I/Os Per Bank for XC3S1600E in the FG320 Package
Package Edge Top Right Bottom Left TOTAL Maximum I/O 61 63 63 63 250 All Possible I/O Pins by Type I/O 33 25 23 38 119 INPUT 13 12 11 12 48 DUAL 1 21 24 0 46 VREF 6 5 5 5 21 GCLK 8 0 0 8 16
I/O Bank 0 1 2 3
Footprint Migration Differences
Table 28 summarizes any footprint and functionality differences between the XC3S500E, the XC3S1200E, and the XC3S1600E FPGAs that may affect easy migration between devices available in the FG320 package. There are 26 such balls. All other pins not listed in Table 28 unconditionally migrate between Spartan-3E devices available in the FG320 package.
The XC3S500E is duplicated on both the left and right sides of the table to show migrations to and from the XC3S1200E and the XC3S1600E. The arrows indicate the direction for easy migration. A double-ended arrow ( ) indicates that the two pins have identical functionality. A left-facing arrow ( ) indicates that the pin on the device on the right unconditionally migrates to the pin on the device on the left. It may be possible to migrate the opposite direction depending on the I/O configuration. For example, an I/O pin (Type = I/O)
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Pinout Descriptions
can migrate to an input-only pin (Type = INPUT) if the I/O pin is configured as an input.
Table 28: FG320 Footprint Migration Differences
Pin A7 A12 D4 D6 D13 E3 E4 E6 E15 E16 E17 F4 N12 N14 N15 P3 P4 P12 P15 P16 R4 U6 U13 V5 V6 V7 Bank 0 0 3 0 0 3 3 0 1 1 1 3 2 1 1 3 3 2 1 1 3 2 2 2 2 2 XC3S500E INPUT N.C. N.C. N.C. INPUT N.C. N.C. N.C. N.C. N.C. I/O I/O N.C. N.C. N.C. N.C. N.C. N.C. I/O N.C. VREF(I/O) INPUT INPUT N.C. N.C. N.C. Migration XC3S1200E I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O INPUT INPUT I/O I/O I/O I/O I/O I/O INPUT I/O VREF(INPUT) I/O I/O I/O VREF I/O Migration XC3S1600E I/O INPUT I/O I/O I/O I/O I/O I/O I/O I/O INPUT INPUT I/O I/O I/O I/O I/O I/O INPUT I/O VREF(INPUT) I/O I/O I/O VREF I/O Migration XC3S500E INPUT N.C. N.C. N.C. INPUT N.C. N.C. N.C. N.C. N.C. I/O I/O N.C. N.C. N.C. N.C. N.C. N.C. I/O N.C. VREF(I/O) INPUT INPUT N.C. N.C. N.C.
DIFFERENCES
Legend:
26
1
26
This pin is identical on both the device on the left and the right. This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be possible depending on how the pin is configured for the device on the right. This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be possible depending on how the pin is configured for the device on the left.
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Pinout Descriptions
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FG320 Footprint
Bank 0
1 A
GND
2
TDI
3
INPUT I/O
4
I/O
L24P_0
5
INPUT
L22P_0
6
I/O
L20N_0
7
INPUT
8
I/O INPUT
9
VCCO_0
10
I/O
L12N_0 GCLK7
11
I/O
12
INPUT
13
I/O
L05P_0
14
I/O
L04N_0
15
INPUT
L02N_0
16
I/O
L01N_0
17
TCK
18
GND
B
PROG_B
GND
L25N_0 HSWAP
I/O
L24N_0
INPUT
L22N_0
I/O
L20P_0
INPUT
L13N_0 GCLK9
I/O
L12P_0 GCLK6
VCCAUX
L13P_0 GCLK8
I/O
VREF_0
I/O
VCCAUX L05N_0 VREF_0
I/O
L04P_0
INPUT
L02P_0
I/O
L01P_0
GND I/O
INPUT I/O
L24P_1 LDC1
C
I/O
L01P_3
I/O
L01N_3
I/O
L25P_0
I/O
I/O
L23P_0
VCCO_0
I/O
L18P_0
INPUT
L16P_0
I/O
L14P_0 GCLK10
GND I/O
L11P_0 GCLK4
I/O
L09P_0
INPUT
L07P_0
I/O
VCCO_0 L03N_0 VREF_0
INPUT
TDO I/O
L24N_1 LDC2
D
I/O
L02P_3
I/O
L02N_3 VREF_3
INPUT I/O
L04N_3
I/O
I/O
L23N_0 VREF_0
I/O
L21P_0
I/O
L18N_0 VREF_0
INPUT
L16N_0
I/O
L14N_0 GCLK11
I/O
L09N_0
INPUT
L07N_0
INPUT
I/O
L03P_0
I/O
L23P_1 HDC
TMS
L23N_1 LDC0
INPUT
VREF_1
E
I/O
L03N_3
I/O
L03P_3
I/O
L04P_3
I/O VCCINT L21N_0
I/O
L19N_0 VREF_0
I/O
L17P_0
I/O
L15P_0
I/O
L11N_0 GCLK5
I/O
L08P_0
I/O
L06N_0
I/O
I/O VCCINT L22P_1
I/O
L22N_1
INPUT
INPUT
F
I/O
L05P_3
I/O
L05N_3
VCCO_3
INPUT
INPUT VCCINT
I/O
L19P_0
I/O
L17N_0
I/O
L15N_0
INPUT
L10P_0
I/O
L08N_0
I/O
L06P_0
VCCINT
I/O
L21N_1
I/O
L21P_1
VCCO_1
I/O
L19N_1
I/O
L19P_1
G
INPUT
VCCAUX
I/O
L06P_3
I/O
L06N_3 VREF_3
I/O
L07N_3
I/O
L07P_3
GND
VCCO_0
I/O
INPUT
L10N_0
VCCO_0
GND
I/O
L20N_1
I/O
L20P_1
I/O
L18P_1
I/O
L18N_1
VCCAUX
INPUT
H
I/O
L10N_3
I/O
L10P_3
I/O
L09N_3
I/O
L09P_3
I/O
L08N_3
I/O
L08P_3
VCCO_3
GND
GND
GND
GND
VCCO_1
INPUT I/O
L15N_1 A1
I/O
L17P_1
I/O
L17N_1
I/O
L16P_1
I/O
L16N_1 A0 L13P_1 A6 RHCLK4 IRDY1
INPUT
VREF_1
I/O
I/O
L12N_3 LHCLK3 IRDY2
I/O GND I/O
L11N_3 LHCLK1
I/O
L11P_3 LHCLK0
J
Bank 3
L12P_3 LHCLK2
VREF_3
INPUT
GND
GND
L15P_1 A2
VCCO_1
I/O
L13N_3 LHCLK5
I/O
L14N_3 LHCLK7
I/O
L14P_3 LHCLK6
I/O INPUT GND GND
L11N_1 A9 RHCLK1 VCCO_1
I/O
L11P_1 A10 RHCLK0
K
VCCO_3
INPUT
L13P_3 LHCLK4 TRDY2
L12N_1 A7 RHCLK3 TRDY1
I/O
I/O
L12P_1 A8 RHCLK2
GND I/O
L09P_1 A12
INPUT I/O
L10N_1 VREF_1
INPUT
L
I/O
L15P_3
I/O
L15N_3
I/O
L16P_3
I/O
L16N_3
I/O
L17N_3 VREF_3
I/O
L17P_3
I/O
VCCO_3
GND
GND I/O
GND I/O
L16P_2 M0
GND
INPUT I/O
INPUT
L09N_1 A11
I/O
L10P_1
M INPUT
VCCAUX
I/O
L18N_3
I/O
L18P_3
I/O
L19P_3
I/O
L19N_3
GND
VCCO_2
L12N_2 D6 GCLK13
VCCO_2
GND I/O
L21P_2
L05N_1 VREF_1
I/O
L05P_1
I/O
L07P_1
I/O
L07N_1
VCCAUX
I/O
L08N_1
N
INPUT
INPUT
VCCO_3
I/O
L20P_3
I/O
L20N_3
VCCINT
I/O
L07P_2
I/O
L09N_2
I/O
L12P_2 D7 GCLK12
I/O
L16N_2 DIN D0
I/O
L18N_2
I/O VCCINT L04N_1 I/O
L22P_2 A23
I/O
L04P_1 VCCO_1
INPUT
I/O
L08P_1
P
I/O
L21N_3
I/O
L21P_3
I/O
L22P_3
I/O
L22N_3
VCCINT
I/O
L05N_2
I/O
L07N_2
I/O
L09P_2
I/O I/O
L15N_2 D1 GCLK3
I/O
L18P_2
I/O
L21N_2
VCCINT I/O
L24N_2 A20
INPUT
I/O
I/O
L06P_1
I/O
L06N_1
R
INPUT
I/O
L23N_3
I/O
L23P_3
INPUT
VREF_3
I/O
L04P_2
I/O
L05P_2
INPUT
L08N_2
I/O
L10P_2
I/O
D5
I/O
L15P_2 D2 GCLK2
I/O
I/O
L20N_2
I/O
L22N_2 A22
I/O
L03P_1
I/O
L03N_1 VREF_1
I/O INPUT I/O
L01N_1 A15 L02P_1 A14
T
I/O
L24N_3
I/O
L24P_3
I/O
L01N_2 INIT_B
I/O
L03N_2 MOSI CSI_B
I/O
L04N_2
VCCO_2
INPUT
L08P_2
I/O
L10N_2
INPUT GND I/O
L13P_2 D4 GCLK14 L14N_2 M2 GCLK1
INPUT
L17P_2
I/O
L20P_2
I/O
VCCO_2 L24P_2 A21
I/O
VREF_2
I/O
L26P_2 VS0 A17
I/O
L02N_1 A13
I/O
I/O
L03P_2 DOUT BUSY
U
INPUT
GND
L01P_2 CSO_B
I/O
VREF_2
INPUT
VCCAUX
INPUT
L11P_2
INPUT
L14P_2 RDWR_B GCLK0 VCCO_2
INPUT
L17N_2
VCCAUX
INPUT
INPUT
L23N_2
I/O
L25N_2 VS1 A18
I/O
L26N_2 CCLK
I/O GND
L01P_1 A16
V
GND
INPUT
INPUT
L02N_2
INPUT
L02P_2
I/O
L06P_2
I/O
L06N_2 VREF_2
I/O
INPUT
L11N_2 VREF_2
I/O
L13N_2 D3 GCLK15
I/O
M1
I/O
L19P_2
I/O
L19N_2 VREF_2
INPUT
L23P_2
I/O
L25P_2 VS2 A19
INPUT
DONE
GND
Bank 2
DS312-4_06_021605
Figure 8: FG320 Package Footprint (top view)
I/O: Unrestricted, general-purpose user I/O INPUT: Unrestricted, general-purpose input pin
46 16 4 28
DUAL: Configuration pin, then possible user-I/O GCLK: User I/O, input, or global buffer input JTAG: Dedicated JTAG port pins GND: Ground
VREF: User I/O or input voltage reference for bank
20 8 8
VCCO: Output voltage supply for bank VCCINT: Internal core supply voltage (+1.2V) VCCAUX: Auxiliary supply voltage (+2.5V)
2 0
52
CONFIG: Dedicated configuration pins N.C.: Not connected
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DS312-4 (v1.1) March 21, 2005 Advance Product Specification
Bank 1
INPUT
I/O
I/O
L14N_1 A3 RHCLK7
I/O
L14P_1 A4 4 RHCLK6
I/O
L13N_1 A5 RHCLK5
I/O
R
Pinout Descriptions
FG400: 400-ball Fine-pitch Ball Grid Array
The 400-ball fine-pitch ball grid array, FG400, supports two different Spartan-3E FPGAs, including the XC3S1200E and the XC3S1600E. Both devices share a common footprint for this package as shown in Table 29 and Figure 9. Table 29 lists all the FG400 package pins. They are sorted by bank number and then by pin name. Pairs of pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier. An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Table 29: FG400 Package Pinout
XC3S1200E XC3S1600E Pin Name IO_L09P_0 IO_L10N_0 IO_L10P_0 IO_L11N_0 IO_L11P_0 IO_L12N_0 IO_L12P_0 IO_L14N_0/GCLK5 IO_L14P_0/GCLK4 IO_L15N_0/GCLK7 IO_L15P_0/GCLK6 IO_L17N_0/GCLK11 IO_L17P_0/GCLK10 IO_L18N_0 IO_L18P_0 IO_L20N_0 IO_L20P_0 IO_L21N_0/VREF_0 IO_L21P_0 IO_L23N_0/VREF_0 IO_L23P_0 IO_L24N_0 IO_L24P_0 IO_L26N_0 IO_L26P_0 IO_L27N_0 IO_L27P_0 IO_L29N_0/VREF_0 IO_L29P_0 IO_L30N_0 IO_L30P_0 IO_L31N_0/HSWAP IO_L31P_0 FG400 Ball A14 B13 C13 C12 D12 E12 F12 G11 F11 E10 E11 A9 A10 F9 E9 C9 D9 B8 B9 F7 F8 A6 A7 B5 B6 D6 C6 C5 D5 A2 B2 D4 C4
Bank 0 0 0 0 0 0 0 0
Type I/O I/O I/O I/O I/O I/O I/O GCLK GCLK GCLK GCLK GCLK GCLK I/O I/O I/O I/O VREF I/O VREF I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O DUAL I/O
Pinout Table
Table 29: FG400 Package Pinout
XC3S1200E XC3S1600E Pin Name IO IO IO IO IO IO IO IO IO IO IO IO/VREF_0 IO_L01N_0 IO_L01P_0 IO_L03N_0/VREF_0 IO_L03P_0 IO_L04N_0 IO_L04P_0 IO_L06N_0 IO_L06P_0 IO_L07N_0 IO_L07P_0 IO_L09N_0/VREF_0 FG400 Ball A3 A8 A12 C7 C10 E8 E13 E16 F13 F14 G7 C11 B17 C17 A18 A19 A17 A16 A15 B15 C14 D14 A13
0 0 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O VREF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Pinout Descriptions
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Table 29: FG400 Package Pinout
XC3S1200E XC3S1600E Pin Name IP IP IP_L02N_0 IP_L02P_0 IP_L05N_0 IP_L05P_0 IP_L08N_0 IP_L08P_0 IP_L10N_0 IP_L10P_0 IP_L13N_0 IP_L13P_0 IP_L16N_0/GCLK9 IP_L16P_0/GCLK8 IP_L19N_0 IP_L19P_0 IP_L22N_0 IP_L22P_0 IP_L25N_0 IP_L25P_0 IP_L28N_0 IP_L28P_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 IO_L01N_1/A15 IO_L01P_1/A16 IO_L02N_1/A13 IO_L02P_1/A14 IO_L03N_1/VREF_1 IO_L03P_1 FG400 Ball B18 E5 C16 D16 D15 C15 E14 E15 G14 G13 B11 B12 G10 H10 G9 G8 C8 D8 E6 E7 A4 A5 B4 B10 B16 D7 D13 F10 U18 U17 T18 T17 V19 U19
Table 29: FG400 Package Pinout
XC3S1200E XC3S1600E Pin Name IO_L04N_1 IO_L04P_1 IO_L05N_1 IO_L05P_1 IO_L06N_1 IO_L06P_1 IO_L07N_1 IO_L07P_1 IO_L08N_1/VREF_1 IO_L08P_1 IO_L09N_1 IO_L09P_1 IO_L10N_1 IO_L10P_1 IO_L11N_1 IO_L11P_1 IO_L12N_1/A11 IO_L12P_1/A12 IO_L13N_1/VREF_1 IO_L13P_1 IO_L14N_1/A9/RHCLK1 IO_L14P_1/A10/RHCLK0 IO_L15N_1/A7/RHCLK3/ TRDY1 IO_L15P_1/A8/RHCLK2 IO_L16N_1/A5/RHCLK5 IO_L16P_1/A6/RHCLK4/ IRDY1 IO_L17N_1/A3/RHCLK7 IO_L17P_1/A4/RHCLK6 IO_L18N_1/A1 IO_L18P_1/A2 FG400 Ball W20 V20 R18 R17 T20 U20 P18 P17 P20 R20 P16 N16 N19 N18 N15 M15 M18 M17 L19 M19 L16 M16 L14 L15 K14 K13 J20 K20 K16 J16
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Type INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT GCLK GCLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT VCCO VCCO VCCO VCCO VCCO VCCO DUAL DUAL DUAL DUAL VREF I/O
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Type I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O DUAL DUAL VREF I/O RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL DUAL DUAL
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Pinout Descriptions
Table 29: FG400 Package Pinout
XC3S1200E XC3S1600E Pin Name IO_L19N_1/A0 IO_L19P_1 IO_L20N_1 IO_L20P_1 IO_L21N_1 IO_L21P_1 IO_L22N_1 IO_L22P_1 IO_L23N_1 IO_L23P_1 IO_L24N_1/VREF_1 IO_L24P_1 IO_L25N_1 IO_L25P_1 IO_L26N_1 IO_L26P_1 IO_L27N_1 IO_L27P_1 IO_L28N_1 IO_L28P_1 IO_L29N_1/LDC0 IO_L29P_1/HDC IO_L30N_1/LDC2 IO_L30P_1/LDC1 IP IP IP IP IP IP IP IP IP IP FG400 Ball J13 J14 J17 J18 H19 J19 H15 H16 H18 H17 H20 G20 G16 F16 F19 F20 F18 F17 D20 E20 D18 E18 C19 C20 B20 G15 G18 H14 J15 L18 M20 N14 N20 P15
Table 29: FG400 Package Pinout
XC3S1200E XC3S1600E Pin Name IP IP IP/VREF_1 IP/VREF_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 IO IO IO IO IO IO IO IO IO/D5 IO/M1 IO/VREF_2 IO/VREF_2 IO_L01N_2/INIT_B IO_L01P_2/CSO_B IO_L03N_2/MOSI/CSI_B IO_L03P_2/DOUT/BUSY IO_L04N_2 IO_L04P_2 IO_L06N_2 IO_L06P_2 IO_L07N_2 IO_L07P_2 IO_L09N_2/VREF_2 IO_L09P_2 FG400 Ball R16 R19 E19 K18 D19 G17 K15 K19 N17 T19 P8 P13 R9 R13 W15 Y5 Y7 Y13 N11 T11 Y3 Y17 V4 U4 V5 U5 Y4 W4 T6 T5 U7 V7 R7 T7
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Type DUAL I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O DUAL DUAL DUAL DUAL INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT
Bank 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Type INPUT INPUT VREF VREF VCCO VCCO VCCO VCCO VCCO VCCO I/O I/O I/O I/O I/O I/O I/O I/O DUAL DUAL VREF VREF DUAL DUAL DUAL DUAL I/O I/O I/O I/O I/O I/O VREF I/O
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Pinout Descriptions
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Table 29: FG400 Package Pinout
XC3S1200E XC3S1600E Pin Name IO_L10N_2 IO_L10P_2 IO_L12N_2 IO_L12P_2 IO_L13N_2 IO_L13P_2 IO_L15N_2/D6/GCLK13 IO_L15P_2/D7/GCLK12 IO_L16N_2/D3/GCLK15 IO_L16P_2/D4/GCLK14 IO_L18N_2/D1/GCLK3 IO_L18P_2/D2/GCLK2 IO_L19N_2/DIN/D0 IO_L19P_2/M0 IO_L21N_2 IO_L21P_2 IO_L22N_2/VREF_2 IO_L22P_2 IO_L24N_2 IO_L24P_2 IO_L25N_2 IO_L25P_2 IO_L27N_2/A22 IO_L27P_2/A23 IO_L28N_2 IO_L28P_2 IO_L30N_2/A20 IO_L30P_2/A21 IO_L31N_2/VS1/A18 IO_L31P_2/VS2/A19 IO_L32N_2/CCLK FG400 Ball V8 W8 U9 V9 Y8 Y9 W10 W9 P10 R10 V11 V10 Y12 Y11 U12 V12 W12 W13 U13 V13 P14 R14 Y14 Y15 T15 U15 V16 U16 Y18 W18 W19
Table 29: FG400 Package Pinout
XC3S1200E XC3S1600E Pin Name IO_L32P_2/VS0/A17 IP IP IP_L02N_2 IP_L02P_2 IP_L05N_2 IP_L05P_2 IP_L08N_2 IP_L08P_2 IP_L11N_2 IP_L11P_2 IP_L14N_2/VREF_2 IP_L14P_2 IP_L17N_2/M2/GCLK1 IP_L17P_2/RDWR_B/ GCLK0 IP_L20N_2 IP_L20P_2 IP_L23N_2/VREF_2 IP_L23P_2 IP_L26N_2 IP_L26P_2 IP_L29N_2 IP_L29P_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 IO_L01N_3 IO_L01P_3 IO_L02N_3/VREF_3 IO_L02P_3 FG400 Ball Y19 T16 W3 Y2 W2 V6 U6 Y6 W6 R8 T8 T10 T9 P12 P11 T12 R12 T13 T14 V14 V15 W16 Y16 R11 U8 U14 W5 W11 W17 D2 D3 E3 E4
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Type I/O I/O I/O I/O I/O I/O DUAL/ GCLK DUAL/ GCLK DUAL/ GCLK DUAL/ GCLK DUAL/ GCLK DUAL/ GCLK DUAL DUAL I/O I/O VREF I/O I/O I/O I/O I/O DUAL DUAL I/O I/O DUAL DUAL DUAL DUAL DUAL
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3
Type DUAL INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT VREF INPUT DUAL/ GCLK DUAL/ GCLK INPUT INPUT VREF INPUT INPUT INPUT INPUT INPUT VCCO VCCO VCCO VCCO VCCO VCCO I/O I/O VREF I/O
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Pinout Descriptions
Table 29: FG400 Package Pinout
XC3S1200E XC3S1600E Pin Name IO_L03N_3 IO_L03P_3 IO_L04N_3 IO_L04P_3 IO_L05N_3 IO_L05P_3 IO_L06N_3 IO_L06P_3 IO_L07N_3 IO_L07P_3 IO_L08N_3 IO_L08P_3 IO_L09N_3/VREF_3 IO_L09P_3 IO_L10N_3 IO_L10P_3 IO_L11N_3 IO_L11P_3 IO_L12N_3 IO_L12P_3 IO_L13N_3 IO_L13P_3 IO_L14N_3/LHCLK1 IO_L14P_3/LHCLK0 IO_L15N_3/LHCLK3/IRDY2 IO_L15P_3/LHCLK2 IO_L16N_3/LHCLK5 IO_L16P_3/LHCLK4/TRDY2 IO_L17N_3/LHCLK7 IO_L17P_3/LHCLK6 IO_L18N_3 IO_L18P_3 IO_L19N_3 IO_L19P_3 FG400 Ball C1 B1 E1 D1 F3 F4 F1 F2 G4 G3 G5 H5 H3 H2 H7 H6 J4 J3 J1 J2 J6 K6 K2 K3 L7 K7 L1 M1 L3 M3 M7 M8 M4 M5
Table 29: FG400 Package Pinout
XC3S1200E XC3S1600E Pin Name IO_L20N_3/VREF_3 IO_L20P_3 IO_L21N_3 IO_L21P_3 IO_L22N_3 IO_L22P_3 IO_L23N_3 IO_L23P_3 IO_L24N_3 IO_L24P_3 IO_L25N_3 IO_L25P_3 IO_L26N_3 IO_L26P_3 IO_L27N_3 IO_L27P_3 IO_L28N_3/VREF_3 IO_L28P_3 IO_L29N_3 IO_L29P_3 IO_L30N_3 IO_L30P_3 IP IP IP IP IP IP IP IP IP IP IP IP FG400 Ball N6 M6 N2 N1 P7 N7 N4 N3 R1 P1 R5 P5 T2 R2 R4 R3 T1 U1 T3 U3 V1 V2 F5 G1 G6 H1 J5 L5 L8 M2 N5 P3 T4 W1
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK I/O I/O I/O I/O
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Type VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT
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Pinout Descriptions
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Table 29: FG400 Package Pinout
XC3S1200E XC3S1600E Pin Name IP/VREF_3 IP/VREF_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND FG400 Ball K5 P6 E2 H4 L2 L6 P4 U2 A1 A11 A20 B7 B14 C3 C18 D10 F6 F15 G2 G12 G19 H8 J9 J11 K1 K8 K10 K12 K17 L4 L9 L11 L13 L20
Table 29: FG400 Package Pinout
XC3S1200E XC3S1600E Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND DONE PROG_B TCK TDI TDO TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT FG400 Ball M10 M12 N13 P2 P9 P19 R6 R15 U11 V3 V18 W7 W14 Y1 Y10 Y20 V17 C2 D17 B3 B19 E17 D11 H12 J7 K4 L17 M14 N9 U10 H9 H11 H13 J8
Bank 3 3 3 3 3 3 3 3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Type VREF VREF VCCO VCCO VCCO VCCO VCCO VCCO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Bank GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT
Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND CONFIG CONFIG JTAG JTAG JTAG JTAG VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT
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Pinout Descriptions
Table 29: FG400 Package Pinout
XC3S1200E XC3S1600E Pin Name VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT FG400 Ball J10 J12 K9 K11 L10 L12 M9 M11
Table 29: FG400 Package Pinout
XC3S1200E XC3S1600E Pin Name VCCINT VCCINT VCCINT VCCINT FG400 Ball M13 N8 N10 N12
Bank VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
Type VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
Bank VCCINT VCCINT VCCINT VCCINT
Type VCCINT VCCINT VCCINT VCCINT
User I/Os by Bank
Table 30 indicates how the 304 available user-I/O pins are distributed between the four I/O banks on the FG400 package.
Table 30: User I/Os Per Bank for the XC3S250E and XC3S500E in the FG400 Package
Package Edge Top Right Bottom Left TOTAL Maximum I/O 78 74 78 74 304 All Possible I/O Pins by Type I/O 43 35 30 48 156 INPUT 20 12 18 12 62 DUAL 1 21 24 0 46 VREF 6 6 6 6 24 GCLK 8 0 0 8 16
I/O Bank 0 1 2 3
Footprint Migration Differences
The XC3S1200E and XC3S1600E FPGAs have identical footprints in the FG400 package. Designs can migrate
between the XC3S1200E and XC3S1600E FPGAs without further consideration.
DS312-4 (v1.1) March 21, 2005 Advance Product Specification
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Pinout Descriptions
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FG400 Footprint
Left Half of Package (top view)
1 A
GND
Bank 0
2
I/O
L30N_0
3
I/O
4
INPUT
L28N_0
5
INPUT
L28P_0
6
I/O
L24N_0
7
I/O
L24P_0
8
I/O I/O
9
I/O
L17N_0 GCLK11
10
I/O
L17P_0 GCLK10
156
I/O: Unrestricted, general-purpose user I/O INPUT: User I/O or reference resistor input for bank DUAL: Configuration pin, then possible user I/O VREF: User I/O or input voltage reference for bank GCLK: User I/O, input, or clock buffer input CONFIG: Dedicated configuration pins JTAG: Dedicated JTAG port pins GND: Ground
B
I/O
L03P_3
I/O
L30P_0
TDI
VCCO_0
I/O
L26N_0
I/O
L26P_0
GND
L21N_0 VREF_0
I/O
L21P_0
VCCO_0
C
I/O
L03N_3
PROG_B
GND
I/O
L31P_0
I/O
L29N_0 VREF_0
I/O
L27P_0
I/O
INPUT
L22N_0
I/O
L20N_0
I/O
62
D
I/O
L04P_3
I/O
L01N_3
I/O
L01P_3
I/O
L31N_0 HSWAP
I/O
L29P_0
I/O
L27N_0
VCCO_0
INPUT
L22P_0
I/O
L20P_0
GND I/O
L15N_0 GCLK7
46 24 16 2 4 42 24 16 8 0
E
I/O
L04N_3
I/O
VCCO_3 L02N_3 VREF_3
I/O
L02P_3
INPUT
INPUT
L25N_0
INPUT
L25P_0
I/O
I/O
L18P_0
F
I/O
L06N_3
I/O
L06P_3
I/O
L05N_3
I/O
L05P_3
I/O INPUT GND
L23N_0 VREF_0
I/O
L23P_0
I/O
L18N_0
VCCO_0
G
INPUT
GND
I/O
L07P_3
I/O
L07N_3
I/O
L08N_3
INPUT
I/O
INPUT
L19P_0
INPUT
L19N_0
INPUT
L16N_0 GCLK9
H
INPUT
I/O
L09P_3
I/O
L09N_3 VREF_3 VCCO_3
I/O
L08P_3
I/O
L10P_3
I/O
L10N_3
INPUT GND VCCINT
L16P_0 GCLK8
J
I/O
L12N_3
I/O
L12P_3
I/O
L11P_3
I/O
L11N_3
INPUT
I/O
L13N_3
VCCAUX
VCCINT
GND
VCCINT
I/O
I/O
L14P_3 LHCLK0 VCCAUX
Bank 3
K
GND I/O
L14N_3 LHCLK1
INPUT
VREF_3
I/O
L13P_3
I/O
L15P_3 LHCLK2
GND
VCCINT
GND
VCCO: Output voltage supply for bank VCCINT: Internal core supply voltage (+1.2V) VCCAUX: Auxiliary supply voltage (+2.5V) N.C.: Not connected
I/O
VCCO_3 L17N_3 LHCLK7
I/O GND INPUT
VCCO_3 L15N_3 LHCLK3 IRDY2
L
L16N_3 LHCLK5
INPUT
GND
VCCINT
I/O
I/O INPUT
L17P_3 LHCLK6
M
L16P_3 LHCLK4 TRDY2
I/O
L19N_3
I/O
L19P_3
I/O
L20P_3
I/O
L18N_3
I/O
L18P_3
VCCINT
GND
N
I/O
L21P_3
I/O
L21N_3
I/O
L23P_3
I/O
L23N_3
I/O INPUT
L20N_3 VREF_3
I/O
L22P_3
VCCINT VCCAUX VCCINT I/O I/O GND
L16N_2 D3 GCLK15
P
I/O
L24P_3
GND
INPUT
VCCO_3
I/O
L25P_3
INPUT
VREF_3
I/O
L22N_3
R
I/O
L24N_3
I/O
L26P_3
I/O
L27P_3
I/O
L27N_3
I/O
L25N_3
I/O GND
L09N_2 VREF_2
INPUT
L11N_2
I/O I/O
L16P_2 D4 GCLK14
I/O
T
L28N_3 VREF_3
I/O
L26N_3
I/O
L29N_3
INPUT I/O
L01P_2 CSO_B
I/O
L06P_2
I/O
L06N_2
I/O
L09P_2
INPUT
L11P_2
INPUT
L14P_2
INPUT
L14N_2 VREF_2
U
I/O
L28P_3
VCCO_3
I/O
L29P_3
I/O
L03P_2 DOUT BUSY
INPUT
L05P_2
I/O
L07N_2
VCCO_2
I/O
L12N_2
VCCAUX
V
I/O
L30N_3
I/O
L30P_3
I/O GND
L01N_2 INIT_B
I/O
L03N_2 MOSI CSI_B VCCO_2
INPUT
L05N_2
I/O
L07P_2
I/O
L10N_2
I/O
L12P_2
I/O
L18P_2 D2 GCLK2
W
INPUT
INPUT
L02P_2
INPUT
I/O
L04P_2
INPUT
L08P_2
GND
I/O
L10P_2
I/O
L15P_2 D7 GCLK12
I/O
L15N_2 D6 GCLK13
Y
GND
INPUT
L02N_2
I/O
VREF_2
I/O
L04N_2
I/O
INPUT
L08N_2
I/O
I/O
L13N_2
I/O
L13P_2
GND
Bank 2
Figure 9: FG400 Package Footprint (top view)
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Pinout Descriptions
Bank 0
11
GND
12
I/O
13
I/O
L09N_0 VREF_0
14
I/O
L09P_0
15
I/O
L06N_0
16
I/O
L04P_0
17
I/O
L04N_0
18
I/O
L03N_0 VREF_0
19
I/O
L03P_0
20
GND
A
Right Half of Package (top view)
INPUT
L13N_0
INPUT
L13P_0
I/O
L10N_0
GND
I/O
L06P_0
VCCO_0
I/O
L01N_0
INPUT
TDO I/O
INPUT I/O
L30P_1 LDC1
B
I/O
VREF_0
I/O
L11N_0
I/O
L10P_0
I/O
L07N_0
INPUT
L05P_0
INPUT
L02N_0
I/O
L01P_0
GND I/O
L30N_1 LDC2
C
VCCAUX
I/O
L11P_0
VCCO_0
I/O
L07P_0
INPUT
L05N_0
INPUT
L02P_0
TCK
L29N_1 LDC0
VCCO_1
I/O
L28N_1
D
I/O
L15P_0 GCLK6
I/O
L12N_0
I/O
INPUT
L08N_0
INPUT
L08P_0
I/O I/O TMS
L29P_1 HDC
INPUT
VREF_1
I/O
L28P_1
E
I/O
L14P_0 GCLK4
I/O
L12P_0
I/O
I/O
GND
I/O
L25P_1
I/O
L27P_1
I/O
L27N_1
I/O
L26N_1
I/O
L26P_1
F
I/O
L14N_0 GCLK5
GND
INPUT
L10P_0
INPUT
L10N_0
INPUT
I/O
L25N_1
VCCO_1
INPUT
GND
I/O
L24P_1
G
VCCINT VCCAUX VCCINT I/O GND VCCINT
L19N_1 A0 L16P_1 A6 RHCLK4 IRDY1
INPUT
I/O
L22N_1
I/O
L22P_1
I/O
L23P_1
I/O
L23N_1
I/O
L21N_1
I/O
L24N_1 VREF_1
H
I/O
L19P_1
I/O INPUT
L18P_1 A2
I/O
L20N_1
I/O
L20P_1
I/O
L21P_1
I/O
L17N_1 A3 RHCLK7
J
I/O
I/O
L16N_1 A5 RHCLK5 L15N_1 A7 RHCLK3 TRDY1 VCCO_1
I/O
L18N_1 A1
VCCINT
GND
GND
VREF_1
VCCO_1
I/O
I/O
L15P_1 A8 RHCLK2
I/O
L14N_1 A9 RHCLK1 VCCAUX
I/O INPUT I/O
L12N_1 A11 L13N_1 VREF_1
GND
VCCINT
GND
GND
L
VCCINT
GND
VCCINT VCCAUX
I/O
L11P_1
I/O
L14P_1 A10 RHCLK0
I/O
L12P_1 A12
I/O
L13P_1
INPUT
M
I/O
D5
VCCINT INPUT
L17N_2 M2 GCLK1
GND
INPUT
I/O
L11N_1
I/O
L09P_1
VCCO_1
I/O
L10P_1
I/O
L10N_1
INPUT I/O
N
INPUT
L17P_2 RDWR_B GCLK0 VCCO_2
I/O
I/O
L25N_2
INPUT
I/O
L09N_1
I/O
L07P_1
I/O
L07N_1
GND
L08N_1 VREF_1
P
INPUT
L20P_2
I/O INPUT
L23N_2 VREF_2
I/O
L25P_2
GND
INPUT
I/O
L05P_1
I/O
L05N_1
INPUT
I/O
L08P_1
R
I/O
M1
INPUT
L20N_2
INPUT
L23P_2
I/O
L28N_2
I/O INPUT I/O
L30P_2 A21 L02P_1 A14
I/O
L02N_1 A13 VCCO_1
I/O
L06N_1
T
GND I/O
L18N_2 D1 GCLK3 VCCO_2
I/O
L21N_2
I/O
L24N_2
VCCO_2
I/O
L28P_2
I/O
L01P_1 A16
I/O
L01N_1 A15
I/O
L03P_1
I/O
L06P_1
U
I/O
L21P_2
I/O
L24P_2
INPUT
L26N_2
INPUT
L26P_2
I/O
L30N_2 A20
I/O DONE GND I/O
VCCO_2 L31P_2 VS2 A19 L03N_1 VREF_1
I/O
L04P_1
V
I/O
L22N_2 VREF_2
I/O
L22P_2
GND I/O
I/O I/O
L27P_2 A23
INPUT
L29N_2
I/O
L32N_2 CCLK
I/O
L04N_1
W
I/O
L19P_2 M0
I/O
L19N_2 DIN D0
I/O
L27N_2 A22
INPUT
L29P_2
I/O
VREF_2
I/O
L31N_2 VS1 A18
I/O
L32P_2 VS0 A17
GND
Y
Bank 2
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Bank 1
INPUT
I/O
L17P_1 A4 RHCLK6
K
61
Pinout Descriptions
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FG484: 484-ball Fine-pitch Ball Grid Array
The 484-ball fine-pitch ball grid array, FG484, supports the XC3S1600E FPGA. Table 31 lists all the FG484 package pins. They are sorted by bank number and then by pin name. Pairs of pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier. An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Table 31: FG484 Package Pinout
Bank 0 0 0 0 0 0 0 XC3S1600E Pin Name IO_L10P_0 IO_L11N_0 IO_L11P_0 IO_L12N_0/VREF_0 IO_L12P_0 IO_L13N_0 IO_L13P_0 IO_L15N_0 IO_L15P_0 IO_L16N_0 IO_L16P_0 IO_L18N_0/GCLK5 IO_L18P_0/GCLK4 IO_L19N_0/GCLK7 IO_L19P_0/GCLK6 IO_L21N_0/GCLK11 IO_L21P_0/GCLK10 IO_L22N_0 IO_L22P_0 IO_L24N_0 IO_L24P_0 IO_L25N_0/VREF_0 IO_L25P_0 IO_L27N_0 IO_L27P_0 IO_L28N_0 IO_L28P_0 IO_L29N_0 IO_L29P_0 IO_L30N_0 IO_L30P_0 IO_L32N_0/VREF_0 IO_L32P_0 IO_L33N_0 FG484 Ball F15 D14 E14 A14 A15 H14 G14 G13 F13 J13 H13 E12 F12 C12 B12 B11 C11 D11 E11 A9 A10 D10 C10 H8 H9 C9 B9 E9 D9 B8 A8 F7 F8 A6 Type I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O GCLK GCLK GCLK GCLK GCLK GCLK I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O
Pinout Table
Table 31: FG484 Package Pinout
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO IO IO IO IO IO IO IO IO IO IO IO/VREF_0 IO_L01N_0 IO_L01P_0 IO_L03N_0/VREF_0 IO_L03P_0 IO_L04N_0 IO_L04P_0 IO_L06N_0 IO_L06P_0 IO_L07N_0 IO_L07P_0 IO_L09N_0/VREF_0 IO_L09P_0 IO_L10N_0 XC3S1600E Pin Name FG484 Ball B6 B13 C5 C14 E16 F9 F16 G8 H10 H15 J11 G12 C18 C19 A20 A21 A19 A18 C16 D16 A16 A17 B15 C15 G15 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Pinout Descriptions
Table 31: FG484 Package Pinout
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XC3S1600E Pin Name IO_L33P_0 IO_L35N_0 IO_L35P_0 IO_L36N_0 IO_L36P_0 IO_L38N_0/VREF_0 IO_L38P_0 IO_L39N_0 IO_L39P_0 IO_L40N_0/HSWAP IO_L40P_0 IP IP IP_L02N_0 IP_L02P_0 IP_L05N_0 IP_L05P_0 IP_L08N_0 IP_L08P_0 IP_L14N_0 IP_L14P_0 IP_L17N_0 IP_L17P_0 IP_L20N_0/GCLK9 IP_L20P_0/GCLK8 IP_L23N_0 IP_L23P_0 IP_L26N_0 IP_L26P_0 IP_L31N_0 IP_L31P_0 IP_L34N_0 IP_L34P_0 IP_L37N_0 IP_L37P_0 FG484 Ball A7 A4 A5 E7 D7 D6 D5 B4 B3 D4 C4 B19 E6 D17 D18 C17 B17 E15 D15 D13 C13 A12 A13 H11 H12 F10 F11 G9 G10 C8 D8 C7 C6 A3 A2 Type I/O I/O I/O I/O I/O VREF I/O I/O I/O DUAL I/O INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT GCLK GCLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT
Table 31: FG484 Package Pinout
Bank 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 XC3S1600E Pin Name VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 IO_L01N_1/A15 IO_L01P_1/A16 IO_L02N_1/A13 IO_L02P_1/A14 IO_L03N_1/VREF_1 IO_L03P_1 IO_L04N_1 IO_L04P_1 IO_L05N_1 IO_L05P_1 IO_L06N_1 IO_L06P_1 IO_L07N_1/VREF_1 IO_L07P_1 IO_L08N_1 IO_L08P_1 IO_L09N_1 IO_L09P_1 IO_L10N_1 IO_L10P_1 IO_L11N_1 IO_L11P_1 IO_L12N_1/VREF_1 IO_L12P_1 IO_L13N_1 IO_L13P_1 IO_L14N_1 IO_L14P_1 FG484 Ball B5 B10 B14 B18 E8 F14 G11 Y22 AA22 W21 Y21 W20 V20 U19 V19 V22 W22 T19 T18 U20 U21 T22 U22 R19 R18 R16 T16 R21 R20 P18 P17 P22 R22 P15 P16 Type VCCO VCCO VCCO VCCO VCCO VCCO VCCO DUAL DUAL DUAL DUAL VREF I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O
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Pinout Descriptions
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Table 31: FG484 Package Pinout
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 XC3S1600E Pin Name IO_L15N_1 IO_L15P_1 IO_L16N_1/A11 IO_L16P_1/A12 IO_L17N_1/VREF_1 IO_L17P_1 IO_L18N_1/A9/RHCLK1 IO_L18P_1/A10/RHCLK0 IO_L19N_1/A7/RHCLK3/ TRDY1 IO_L19P_1/A8/RHCLK2 IO_L20N_1/A5/RHCLK5 IO_L20P_1/A6/RHCLK4/ IRDY1 IO_L21N_1/A3/RHCLK7 IO_L21P_1/A4/RHCLK6 IO_L22N_1/A1 IO_L22P_1/A2 IO_L23N_1/A0 IO_L23P_1 IO_L24N_1 IO_L24P_1 IO_L25N_1 IO_L25P_1 IO_L26N_1 IO_L26P_1 IO_L27N_1 IO_L27P_1 IO_L28N_1/VREF_1 IO_L28P_1 IO_L29N_1 IO_L29P_1 FG484 Ball N18 N19 N16 N17 M20 N20 M22 N22 M16 M15 L21 L20 L19 L18 K22 L22 K17 K16 K19 K18 K15 J15 J20 J21 J17 J18 H21 H22 H20 H19 Type I/O I/O DUAL DUAL VREF I/O RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL RHCLK/ DUAL DUAL DUAL DUAL I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O
Table 31: FG484 Package Pinout
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 XC3S1600E Pin Name IO_L30N_1 IO_L30P_1 IO_L31N_1 IO_L31P_1 IO_L32N_1 IO_L32P_1 IO_L33N_1 IO_L33P_1 IO_L34N_1 IO_L34P_1 IO_L35N_1 IO_L35P_1 IO_L36N_1 IO_L36P_1 IO_L37N_1/LDC0 IO_L37P_1/HDC IO_L38N_1/LDC2 IO_L38P_1/LDC1 IP IP IP IP IP IP IP IP IP IP IP IP IP IP IP IP IP/VREF_1 FG484 Ball H17 G17 F22 G22 F20 G20 G18 G19 D22 E22 F19 F18 E20 E19 C21 C22 B21 B22 D20 F21 G16 H16 J16 J22 K20 L15 M18 N15 N21 P20 R15 T17 T20 U18 D21 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O DUAL DUAL DUAL DUAL INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT VREF
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Pinout Descriptions
Table 31: FG484 Package Pinout
Bank 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 XC3S1600E Pin Name IP/VREF_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 IO IO IO IO IO IO IO IO IO/D5 IO/M1 IO/VREF_2 IO/VREF_2 IO_L01N_2/INIT_B IO_L01P_2/CSO_B IO_L03N_2/MOSI/CSI_B IO_L03P_2/DOUT/BUSY IO_L04N_2 IO_L04P_2 IO_L06N_2 IO_L06P_2 IO_L07N_2 IO_L07P_2 IO_L09N_2/VREF_2 IO_L09P_2 IO_L10N_2 IO_L10P_2 IO_L11N_2 FG484 Ball L17 E21 H18 K21 L16 P21 R17 V21 Y8 Y9 AA10 AB5 AB13 AB14 AB16 AB18 AB11 AA12 AB4 AB21 AB3 AA3 Y5 W5 W6 V6 W7 Y7 U7 V7 V8 W8 T8 U8 AB8 Type VREF VCCO VCCO VCCO VCCO VCCO VCCO VCCO I/O I/O I/O I/O I/O I/O I/O I/O DUAL DUAL VREF VREF DUAL DUAL DUAL DUAL I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O
Table 31: FG484 Package Pinout
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 XC3S1600E Pin Name IO_L11P_2 IO_L12N_2 IO_L12P_2 IO_L13N_2/VREF_2 IO_L13P_2 IO_L14N_2 IO_L14P_2 IO_L16N_2 IO_L16P_2 IO_L17N_2 IO_L17P_2 IO_L19N_2/D6/GCLK13 IO_L19P_2/D7/GCLK12 IO_L20N_2/D3/GCLK15 IO_L20P_2/D4/GCLK14 IO_L22N_2/D1/GCLK3 IO_L22P_2/D2/GCLK2 IO_L23N_2/DIN/D0 IO_L23P_2/M0 IO_L25N_2 IO_L25P_2 IO_L26N_2/VREF_2 IO_L26P_2 IO_L27N_2 IO_L27P_2 IO_L28N_2 IO_L28P_2 IO_L29N_2 IO_L29P_2 IO_L30N_2 IO_L30P_2 FG484 Ball AA8 W9 V9 R9 T9 AB9 AB10 U10 T10 R10 P10 U11 V11 T11 R11 W12 Y12 U12 V12 Y13 W13 U14 U13 T14 R14 Y14 AA14 W14 V14 AB15 AA15 Type I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O DUAL/ GCLK DUAL/ GCLK DUAL/ GCLK DUAL/ GCLK DUAL/ GCLK DUAL/ GCLK DUAL DUAL I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O
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Pinout Descriptions
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Table 31: FG484 Package Pinout
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 XC3S1600E Pin Name IO_L32N_2 IO_L32P_2 IO_L33N_2 IO_L33P_2 IO_L35N_2/A22 IO_L35P_2/A23 IO_L36N_2 IO_L36P_2 IO_L38N_2/A20 IO_L38P_2/A21 IO_L39N_2/VS1/A18 IO_L39P_2/VS2/A19 IO_L40N_2/CCLK IO_L40P_2/VS0/A17 IP IP IP_L02N_2 IP_L02P_2 IP_L05N_2 IP_L05P_2 IP_L08N_2 IP_L08P_2 IP_L15N_2 IP_L15P_2 IP_L18N_2/VREF_2 IP_L18P_2 IP_L21N_2/M2/GCLK1 IP_L21P_2/RDWR_B/ GCLK0 IP_L24N_2 IP_L24P_2 IP_L31N_2/VREF_2 IP_L31P_2 IP_L34N_2 IP_L34P_2 FG484 Ball W15 Y15 U16 V16 AB17 AA17 W17 Y17 Y18 W18 AA20 AB20 W19 Y19 V17 AB2 AA4 Y4 Y6 AA6 AB7 AB6 Y10 W10 AA11 Y11 P12 R12 R13 T13 T15 U15 Y16 W16 Type I/O I/O I/O I/O DUAL DUAL I/O I/O DUAL DUAL DUAL DUAL DUAL DUAL INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT VREF INPUT DUAL/ GCLK DUAL/ GCLK INPUT INPUT VREF INPUT INPUT INPUT
Table 31: FG484 Package Pinout
Bank 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 XC3S1600E Pin Name IP_L37N_2 IP_L37P_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 IO_L01N_3 IO_L01P_3 IO_L02N_3/VREF_3 IO_L02P_3 IO_L03N_3 IO_L03P_3 IO_L04N_3 IO_L04P_3 IO_L05N_3 IO_L05P_3 IO_L06N_3 IO_L06P_3 IO_L07N_3 IO_L07P_3 IO_L08N_3/VREF_3 IO_L08P_3 IO_L09N_3 IO_L09P_3 IO_L10N_3 IO_L10P_3 IO_L11N_3 IO_L11P_3 IO_L12N_3 IO_L12P_3 IO_L13N_3/VREF_3 IO_L13P_3 FG484 Ball AA19 AB19 T12 U9 V15 AA5 AA9 AA13 AA18 C1 C2 D2 D3 E3 E4 E1 D1 F4 F3 G5 G4 F1 G1 G6 G7 H4 H5 H2 H3 H1 J1 J6 J5 J3 K3 Type INPUT INPUT VCCO VCCO VCCO VCCO VCCO VCCO VCCO I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O
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Pinout Descriptions
Table 31: FG484 Package Pinout
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 XC3S1600E Pin Name IO_L14N_3 IO_L14P_3 IO_L15N_3 IO_L15P_3 IO_L16N_3 IO_L16P_3 IO_L17N_3 IO_L17P_3 IO_L18N_3/LHCLK1 IO_L18P_3/LHCLK0 IO_L19N_3/LHCLK3/IRDY2 IO_L19P_3/LHCLK2 IO_L20N_3/LHCLK5 IO_L20P_3/LHCLK4/TRDY2 IO_L21N_3/LHCLK7 IO_L21P_3/LHCLK6 IO_L22N_3 IO_L22P_3 IO_L23N_3 IO_L23P_3 IO_L24N_3/VREF_3 IO_L24P_3 IO_L25N_3 IO_L25P_3 IO_L26N_3 IO_L26P_3 IO_L27N_3 IO_L27P_3 IO_L28N_3 IO_L28P_3 IO_L29N_3 IO_L29P_3 IO_L30N_3 IO_L30P_3 IO_L31N_3 FG484 Ball J8 K8 K4 K5 K1 L1 L7 K7 L5 M5 M8 L8 N1 M1 M4 M3 N6 N7 P8 N8 N4 N5 P2 P1 R7 P7 P6 P5 R2 R1 R3 R4 T6 R6 U2 Type I/O I/O I/O I/O I/O I/O I/O I/O LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK LHCLK I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Table 31: FG484 Package Pinout
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 XC3S1600E Pin Name IO_L31P_3 IO_L32N_3 IO_L32P_3 IO_L33N_3 IO_L33P_3 IO_L34N_3 IO_L34P_3 IO_L35N_3 IO_L35P_3 IO_L36N_3/VREF_3 IO_L36P_3 IO_L37N_3 IO_L37P_3 IO_L38N_3 IO_L38P_3 IP IP IP IP IP IP IP IP IP IP IP IP IP IP IP IP IP/VREF_3 IP/VREF_3 VCCO_3 VCCO_3 FG484 Ball U1 T4 T5 W1 V1 U4 U3 V4 V3 W3 W2 Y2 Y1 AA1 AA2 F2 F5 G3 H7 J7 K2 K6 M2 M6 N3 P3 R8 T1 T7 U5 W4 L3 T3 E2 H6 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT VREF VREF VCCO VCCO
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Pinout Descriptions
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Table 31: FG484 Package Pinout
Bank 3 3 3 3 3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND XC3S1600E Pin Name VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND FG484 Ball J2 M7 N2 R5 V2 A1 A11 A22 B7 B16 C3 C20 E10 E13 F6 F17 G2 G21 J4 J9 J12 J14 J19 K10 K12 L2 L6 L9 L13 M10 M14 M17 M21 N11 N13 Type VCCO VCCO VCCO VCCO VCCO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Table 31: FG484 Package Pinout
Bank GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND XC3S1600E Pin Name FG484 Ball P4 P9 P11 P14 P19 T2 T21 U6 U17 V10 V13 Y3 Y20 AA7 AA16 AB1 AB12 AB22 AA21 B1 E17 B2 B20 D19 D12 E5 E18 K14 L4 M19 N9 V5 V18 W11 J10 Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND CONFIG CONFIG JTAG JTAG JTAG JTAG VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT
VCCAUX DONE VCCAUX PROG_B VCCAUX TCK VCCAUX TDI VCCAUX TDO VCCAUX TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT
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Pinout Descriptions
Table 31: FG484 Package Pinout
Bank VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT XC3S1600E Pin Name FG484 Ball K9 K11 K13 L10 L11 L12 L14 M9 M11 M12 Type VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
Table 31: FG484 Package Pinout
Bank VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT XC3S1600E Pin Name FG484 Ball M13 N10 N12 N14 P13 Type VCCINT VCCINT VCCINT VCCINT VCCINT
User I/Os by Bank
Table 32 indicates how the 304 available user-I/O pins are distributed between the four I/O banks on the FG484 package.
Table 32: User I/Os Per Bank for the XC3S1600E in the FG484 Package
Package Edge Top Right Bottom Left TOTAL Maximum I/O 94 94 94 94 376 All Possible I/O Pins by Type I/O 56 50 45 63 214 INPUT 22 16 18 16 72 DUAL 1 21 24 0 46 VREF 7 7 7 7 28 GCLK 8 0 0 8 16
I/O Bank 0 1 2 3
Footprint Migration Differences
The XC3S1600E FPGA is the only Spartan-3E device offered in the FG484 package.
DS312-4 (v1.1) March 21, 2005 Advance Product Specification
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Pinout Descriptions
R
FG484 Footprint
Left Half of Package (top view)
1 A
GND
Bank 0
2
INPUT
L37P_0
3
INPUT
L37N_0
4
I/O
L35N_0
5
I/O
L35P_0
6
I/O
L33N_0
7
I/O
L33P_0
8
I/O
L30P_0
9
I/O
L24N_0
10
I/O
L24P_0
11
GND I/O
B
PROG_B
TDI
I/O
L39P_0
I/O
L39N_0
VCCO_0
I/O
GND
I/O
L30N_0
I/O
L28P_0
VCCO_0
L21N_0 GCLK11
214
I/O: Unrestricted, general-purpose user I/O INPUT: User I/O or reference resistor input for bank DUAL: Configuration pin, then possible user I/O VREF: User I/O or input voltage reference for bank GCLK: User I/O, input, or clock buffer input
C
I/O
L01N_3
I/O
L01P_3
GND
I/O
L40P_0
I/O
INPUT
L34P_0
INPUT
L34N_0
INPUT
L31N_0
I/O
L28N_0
I/O
L25P_0
I/O
L21P_0 GCLK10
72
D
I/O
L04P_3
I/O
L02N_3 VREF_3
I/O
L02P_3
I/O
L40N_0 HSWAP
I/O
L38P_0
I/O
L38N_0 VREF_0
I/O
L36P_0
INPUT
L31P_0
I/O
L29P_0
I/O
L25N_0 VREF_0
I/O
L22N_0
46 28 16 2 4 48 28 16 10 0
E
I/O
L04N_3
VCCO_3
I/O
L03N_3
I/O
L03P_3
VCCAUX
INPUT
I/O
L36N_0
VCCO_0
I/O
L29N_0
GND
I/O
L22P_0
F
I/O
L07N_3
INPUT
I/O
L05P_3
I/O
L05N_3
I/O INPUT GND I/O
L08N_3 VREF_3 L32N_0 VREF_0
I/O
L32P_0
I/O
INPUT
L23N_0
INPUT
L23P_0
G
I/O
L07P_3
GND
INPUT
I/O
L06P_3
I/O
L06N_3
I/O
L08P_3
I/O
INPUT
L26N_0
INPUT
L26P_0
VCCO_0
H
I/O
L11N_3
I/O
L10N_3
I/O
L10P_3
I/O
L09N_3
I/O
L09P_3
VCCO_3
INPUT
I/O
L27N_0
I/O
L27P_0
INPUT I/O
L20N_0 GCLK9
CONFIG: Dedicated configuration pins JTAG: Dedicated JTAG port pins GND: Ground
J
I/O
L11P_3
I/O
VCCO_3 L13N_3 VREF_3
GND
I/O
L12P_3
I/O
L12N_3
INPUT
I/O
L14N_3
GND
VCCINT
I/O
K
I/O
L16N_3
INPUT
I/O
L13P_3
I/O
L15N_3
I/O
L15P_3
INPUT
I/O
L17P_3
I/O
L14P_3
VCCINT
GND
VCCINT
Bank 3
L
I/O
L16P_3
GND
INPUT
VREF_3
I/O
VCCAUX L18N_3 LHCLK1
GND
I/O
L17N_3
I/O
L19P_3 LHCLK2
GND
VCCINT VCCINT
VCCO: Output voltage supply for bank VCCINT: Internal core supply voltage (+1.2V) VCCAUX: Auxiliary supply voltage (+2.5V) N.C.: Not connected
I/O
I/O INPUT
L21P_3 LHCLK6
I/O
L21N_3 LHCLK7
I/O
L18P_3 LHCLK0
I/O INPUT
VCCO_3 L19N_3 LHCLK3 IRDY2
M
L20P_3 LHCLK4 TRDY2
VCCINT
GND
VCCINT
I/O
I/O
VCCO_3
N
L20N_3 LHCLK5
INPUT
L24N_3 VREF_3
I/O
L24P_3
I/O
L22N_3
I/O
L22P_3
I/O
L23P_3
VCCAUX
VCCINT
GND
P
I/O
L25P_3
I/O
L25N_3
INPUT
GND
I/O
L27P_3
I/O
L27N_3
I/O
L26P_3
I/O
L23N_3
GND I/O
I/O
L17P_2
GND I/O
L20P_2 D4 GCLK14
R
I/O
L28P_3
I/O
L28N_3
I/O
L29N_3
I/O
L29P_3
VCCO_3
I/O
L30P_3
I/O
L26N_3
INPUT
L13N_2 VREF_2
I/O
L17N_2
T
INPUT
GND
INPUT
VREF_3
I/O
L32N_3
I/O
L32P_3
I/O
L30N_3
INPUT
I/O
L10N_2
I/O
L13P_2
I/O
L16P_2
I/O
L20N_2 D3 GCLK15
U
I/O
L31P_3
I/O
L31N_3
I/O
L34P_3
I/O
L34N_3
INPUT
GND
I/O
L07N_2
I/O
L10P_2
VCCO_2
I/O
L16N_2
I/O
L19N_2 D6 GCLK13
V
I/O
L33P_3
VCCO_3
I/O
L35P_3
I/O
L35N_3
VCCAUX
I/O
L04P_2
I/O
L07P_2
I/O
L09N_2 VREF_2
I/O
L12P_2
I/O GND
L19P_2 D7 GCLK12 VCCAUX
W
I/O
L33N_3
I/O
L36P_3
I/O
L36N_3 VREF_3
I/O INPUT
L03P_2 DOUT BUSY
I/O
L04N_2
I/O
L06N_2
I/O
L09P_2
I/O
L12N_2
INPUT
L15P_2
Y A A A B
I/O
L37P_3
I/O
L37N_3
GND I/O
L01P_2 CSO_B
INPUT
L02P_2
I/O
L03N_2 MOSI CSI_B VCCO_2
INPUT
L05N_2
I/O
L06P_2
I/O
I/O
INPUT
L15N_2
INPUT
L18P_2
I/O
L38N_3
I/O
L38P_3
INPUT
L02N_2
INPUT
L05P_2
GND
I/O
L11P_2
INPUT
VCCO_2
I/O
L18N_2 VREF_2
I/O GND INPUT
L01N_2 INIT_B
I/O
VREF_2
I/O
INPUT
L08P_2
INPUT
L08N_2
I/O
L11N_2
I/O
L14N_2
I/O
L14P_2
I/O
D5
Bank 2
DS312_10_031105
Figure 10: FG484 Package Footprint (top view)
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Pinout Descriptions
Bank 0
12
INPUT
L17N_0
13
INPUT
L17P_0
14
I/O
L12N_0 VREF_0
15
I/O
L12P_0
16
I/O
L07N_0
17
I/O
L07P_0
18
I/O
L04P_0
19
I/O
L04N_0
20
I/O
L03N_0 VREF_0
21
I/O
L03P_0
22
GND I/O
L38P_1 LDC1
A
Right Half of Package (top view)
I/O
L19P_0 GCLK6
I/O I/O
VCCO_0 L09N_0 VREF_0
GND
INPUT
L05P_0
I/O
VCCO_0
INPUT
TDO
L38N_1 LDC2
B
I/O
L19N_0 GCLK7
INPUT
L14P_0
I/O
I/O
L09P_0
I/O
L06N_0
INPUT
L05N_0
I/O
L01N_0
I/O
L01P_0
I/O GND
L37N_1 LDC0
I/O
L37P_1 HDC
C
VCCAUX
INPUT
L14N_0
I/O
L11N_0
INPUT
L08P_0
I/O
L06P_0
INPUT
L02N_0
INPUT
L02P_0
TMS
INPUT
INPUT
VREF_1
I/O
L34N_1
D
I/O
L18N_0 GCLK5
GND
I/O
L11P_0
INPUT
L08N_0
I/O
TCK
VCCAUX
I/O
L36P_1
I/O
L36N_1
VCCO_1
I/O
L34P_1
E
I/O
L18P_0 GCLK4
I/O
L15P_0
VCCO_0
I/O
L10P_0
I/O
GND
I/O
L35P_1
I/O
L35N_1
I/O
L32N_1
INPUT
I/O
L31N_1
F
I/O
VREF_0
I/O
L15N_0
I/O
L13P_0
I/O
L10N_0
INPUT
I/O
L30P_1
I/O
L33N_1
I/O
L33P_1
I/O
L32P_1
GND I/O
L28N_1 VREF_1
I/O
L31P_1
G
INPUT
L20P_0 GCLK8
I/O
L16P_0
I/O
L13N_0
I/O
INPUT
I/O
L30N_1
VCCO_1
I/O
L29P_1
I/O
L29N_1
I/O
L28P_1
H
GND
I/O
L16N_0
GND
I/O
L25P_1
INPUT
I/O
L27N_1
I/O
L27P_1
GND
I/O
L26N_1
I/O
L26P_1
INPUT I/O
J
GND
VCCINT VCCAUX
I/O
L25N_1
I/O
L23P_1
I/O
L23N_1 A0
I/O
L24P_1
I/O
L24N_1
INPUT I/O
VCCO_1
L22N_1 A1
K
VCCINT
GND
VCCINT INPUT I/O
VCCO_1
VREF_1
L22P_1 A2
VCCINT VCCINT
GND
L19P_1 A8 RHCLK2
L19N_1 A7 RHCLK3 TRDY1
I/O
I/O GND I/O
L16P_1 A12
I/O GND
L18N_1 A9 RHCLK1
INPUT
VCCAUX
L17N_1 VREF_1
M
I/O VCCINT INPUT
L21N_2 M2 GCLK1
GND
VCCINT INPUT
L16N_1 A11
I/O
L15N_1
I/O
L15P_1
I/O
L17P_1
I/O INPUT
L18P_1 A10 RHCLK0
N
VCCINT
GND
I/O
L14N_1
I/O
L14P_1
I/O
L12P_1
I/O
L12N_1 VREF_1
GND
INPUT
VCCO_1
I/O
L13N_1
P
INPUT
L21P_2 RDWR_B GCLK0 VCCO_2
INPUT
L24N_2
I/O
L27P_2
INPUT INPUT
L31N_2 VREF_2
I/O
L10N_1
VCCO_1
I/O
L09P_1
I/O
L09N_1
I/O
L11P_1
I/O
L11N_1
I/O
L13P_1
R
INPUT
L24P_2
I/O
L27N_2
I/O
L10P_1
INPUT
I/O
L06P_1
I/O
L06N_1
INPUT I/O
L07N_1 VREF_1
GND
I/O
L08N_1
T
I/O
L23N_2 DIN D0
I/O
L26P_2
I/O
L26N_2 VREF_2
INPUT
L31P_2
I/O
L33N_2
GND
INPUT
I/O
L04N_1
I/O
L07P_1
I/O
L08P_1
U
I/O
L23P_2 M0
GND
I/O
L29P_2
VCCO_2
I/O
L33P_2
INPUT
VCCAUX
I/O
L04P_1
I/O
L03P_1
VCCO_1
I/O
L05N_1
V
I/O
L22N_2 D1 GCLK3
I/O
L25P_2
I/O
L29N_2
I/O
L32N_2
INPUT
L34P_2
I/O
L36N_2
I/O
L38P_2 A21
I/O
L40N_2 CCLK
I/O
L03N_1 VREF_1
I/O
L02N_1 A13
I/O
L05P_1
W
I/O
L22P_2 D2 GCLK2
I/O
L25N_2
I/O
L28N_2
I/O
L32P_2
INPUT
L34N_2
I/O
L36P_2
I/O
L38N_2 A20
I/O
L40P_2 VS0 A17
I/O GND I/O
L39N_2 VS1 A18 L02P_1 A14
I/O
L01N_1 A15
Y A A A B
I/O
M1
VCCO_2
I/O
L28P_2
I/O
L30P_2
I/O GND
L35P_2 A23 VCCO_2
INPUT
L37N_2
I/O DONE
L01P_1 A16
GND
I/O
I/O
I/O
L30N_2
I/O I/O
L35N_2 A22
I/O
INPUT
L37P_2
I/O
L39P_2 VS2 A19
I/O
VREF_2
GND
Bank 2
DS312_11_031105
DS312-4 (v1.1) March 21, 2005 Advance Product Specification
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Bank 1
INPUT
I/O
L21P_1 A4 RHCLK6
I/O
L21N_1 A3 RHCLK7
L20P_1 A6 RHCLK4 IRDY1
I/O
L20N_1 A5 RHCLK5
I/O
L
71
Pinout Descriptions
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Revision History
The following table shows the revision history for this document. Date 03/01/05 03/21/05 Version 1.0 1.1 Initial Xilinx release. Added XC3S250E in the CP132 package to Table 6. Corrected number of differential I/O pairs on CP132. Added pinout and footprint information for the CP132, FG400, and FG484 packages. Removed IRDY and TRDY pins from the VQ100, TQ144, and PQ208 packages. Revision
The Spartan-3E Family Data Sheet
DS312-1, Spartan-3E FPGA Family: Introduction and Ordering Information (Module 1) DS312-2, Spartan-3E FPGA Family: Functional Description (Module 2) DS312-3, Spartan-3E FPGA Family: DC and Switching Characteristics (Module 3) DS312-4, Spartan-3E FPGA Family: Pinout Descriptions (Module 4)
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